chip [ 1229 , 1230 ]
cell 1 pos [ 200 , 200 ] size [ 211 , 217 ]
  name C1SwX1N10 side w offset 103
  name C1SwX0N1 side w offset 50
  name C1SsX1N11 side s offset 100
  name C1SsX0N16 side s offset 50
  name C1SeX1N11 side e offset 104
  name C1SeX0N13 side e offset 50
  name C1SnX1N8 side n offset 100
  name C1SnX0N15 side n offset 50
cell 2 pos [ 811 , 200 ] size [ 202 , 205 ]
  name C2SwX1N12 side w offset 101
  name C2SsX1N15 side s offset 100
  name C2SsX0N4 side s offset 50
  name C2SeX1N7 side e offset 100
  name C2SnX1N9 side n offset 100
  name C2SnX0N14 side n offset 50
cell 3 pos [ 200 , 817 ] size [ 217 , 213 ]
  name C3SwX1N5 side w offset 100
  name C3SwX0N10 side w offset 50
  name C3SsX1N7 side s offset 104
  name C3SeX1N1 side e offset 103
  name C3SeX0N9 side e offset 50
  name C3SnX1N4 side n offset 100
  name C3SnX0N13 side n offset 50
cell 4 pos [ 817 , 805 ] size [ 212 , 211 ]
  name C4SwX1N16 side w offset 100
  name C4SwX0N12 side w offset 50
  name C4SsX1N8 side s offset 100
  name C4SsX0N6 side s offset 50
  name C4SeX1N10 side e offset 102
  name C4SeX0N14 side e offset 50
  name C4SnX1N6 side n offset 102
  name C4SnX0N5 side n offset 50
net tie C1SsX0N16 tie C4SwX1N16
net tie C2SsX1N15 tie C1SnX0N15
net tie C4SeX0N14 tie C2SnX0N14
net tie C1SeX0N13 tie C3SnX0N13
net tie C2SwX1N12 tie C4SwX0N12
net tie C1SeX1N11 tie C1SsX1N11
net tie C3SwX0N10 tie C4SeX1N10 tie C1SwX1N10
net tie C3SeX0N9 tie C2SnX1N9
net tie C1SnX1N8 tie C4SsX1N8
net tie C2SeX1N7 tie C3SsX1N7
net tie C4SnX1N6 tie C4SsX0N6
net tie C3SwX1N5 tie C4SnX0N5
net tie C3SnX1N4 tie C2SsX0N4
net tie C3SeX1N1 tie C1SwX0N1
end