-- Lambda-relative NMOS model for Chipmonk extractor

-- last modified by McCreight, April 6, 1982  3:46 PM
-- taken from Wilhelm's SimDefsFile of October 27, 1981  10:06 AM

library[mosmodels];
library[stdfunctions];

circuit[Lambda _ 2.0] = {

!thyme.models

-- ICL NMOS parameters from Don Nelson's memo of 10/26/81
-- gate length reduction by Scharfetter, March 11, 1982  3:35 PM

  Vdd: node;

  ETran:  circuit[gate, source, drain | L _ 2, W _ 4] = {
    T:  FET[gate, source, drain, Gnd |
      Vt _ 0.7, L _ L*Lambda-0.8, -- due to junction depth
      W _ W*Lambda, Kp _ 37uA, Kb _ 0.4]};
    -- n-channel enhancement-mode transistor

  DTran:  circuit[gate, source, drain | L _ 4, W _ 2] = {
    T:  FET[gate, source, drain, Gnd |
      Vt _ -3.0, L _ L*Lambda-0.8,
      W _ W*Lambda, Kp _ 30uA, Kb _ 0.7]};
    -- n-channel depletion-mode transistor

  Stray:  circuit[n |
      a2M _ 0, p2M _ 0, aM _ 0, pM _ 0,
      aP _ 0, pP _ 0, aD _ 0, pD _ 0, 
      aM2C _ 2.6e-5pF, -- /(uM)^2
      pM2C _ 0, -- /uM
      aMC _ 2.6e-5pF, pMC _ 0,
      aPC _ 4e-5pF, pPC _ 0,
      aDC _ 5.4e-5pF, pDC _ 9.5e-5pF ] = {
    cStray:  capacitor[n, Gnd] = Lambda*
      (Lambda*(a2M*aM2C+aM*aMC+aP*aPC+aD*aDC)+
      p2M*pM2C+pM*pMC+pP*pPC+pD*pDC)};

  powerSupply: voltage[Vdd, Gnd] = 5.0;
(635)