-- Lambda-relative NMOS model for Chipmonk extractor

-- last modified by McCreight, April 6, 1982 3:46 PM
-- taken from Wilhelm’s SimDefsFile of October 27, 1981 10:06 AM

library[mosmodels];
library[stdfunctions];

circuit[Lambda ← 2.0] = {

!thyme.models

-- ICL NMOS parameters from Don Nelson’s memo of 10/26/81
-- gate length reduction by Scharfetter, March 11, 1982 3:35 PM

Vdd: node;

ETran: circuit[gate, source, drain | L ← 2, W ← 4] = {
T: FET[gate, source, drain, Gnd |
Vt ← 0.7, L ← L*Lambda-0.8, -- due to junction depth
W ← W*Lambda, Kp ← 37uA, Kb ← 0.4]};
-- n-channel enhancement-mode transistor

DTran: circuit[gate, source, drain | L ← 4, W ← 2] = {
T: FET[gate, source, drain, Gnd |
Vt ← -3.0, L ← L*Lambda-0.8,
W ← W*Lambda, Kp ← 30uA, Kb ← 0.7]};
-- n-channel depletion-mode transistor

Stray: circuit[n |
a2M ← 0, p2M ← 0, aM ← 0, pM ← 0,
aP ← 0, pP ← 0, aD ← 0, pD ← 0,
aM2C ← 2.6e-5pF, -- /(uM)↑2
pM2C ← 0, -- /uM
aMC ← 2.6e-5pF, pMC ← 0,
aPC ← 4e-5pF, pPC ← 0,
aDC ← 5.4e-5pF, pDC ← 9.5e-5pF ] = {
cStray: capacitor[n, Gnd] = Lambda*
(Lambda*(a2M*aM2C+aM*aMC+aP*aPC+aD*aDC)+
p2M*pM2C+pM*pMC+pP*pPC+pD*pDC)};

powerSupply: voltage[Vdd, Gnd] = 5.0;