cellsoperation.bravo
April 28, 1982  3:31 PM
W Crowther

OPERATING INSTRUCTIONS:

   Make a text file containing the equations for your circuit
       (name it ***.txt)

   Get a copy of chipmonk and a cells.chipbcd on your disk.

   Run chipmonk - invoke cells with ctl/Tab/Semi - and enter the name of your equation file (without the extension).

   The circuit will appear in chipmonk, after a pause.

CREATING A CELLS.CHIPBCD

   While normally you won't have to do this, it may be useful to know how to generate one from the sources. The "cells" system sources and command files are kept in a dump file called cells.dm. Retrieve this file (which contains copies of pp*defs.bcd). Verify that the boolean constant "chip" defined in cellsdefs is TRUE (FALSE is a debugging mode), then bind and compile the sources by executing the lines

    com cells/bln cells2/bln cells6/bln cellstry/bln
    bind cells.chipbcd _ cells.config/cs

And you are ready to go.


FORMAT FOR THE TXT FILE (see example at end)

   Empty lines and lines beginning with -- are ignored

   The body of the file consists of a number of equations consisting of a few key words, some punctuation, and user generated ids. Id's may contain numbers, letters, single-quote, plus and minus, left and right parentheses, back arrows, and generally any printing symbols which are not otherwise used by the program.

   Equation type nor:

    id = nor [ id id ... id ]

  (the first id is the nor of the others, no limit to the number of others as long as there is at least one). If you choose, you can separate the id's with commas. The program treats comma like a space.

   Equation type pass

    id1 = pass [ id2 id3]

Here there must be exactly three id's. id2 is the controlling (red)(gate) signal, and id1 and id3 are interchangable.

   Equation type wire

    id1 = wire [ id id ... id ] 

This equation says that id1 is the wire or of the other id's. What this really means is that all the id's involved in this equation are really the same signal, and in the final diagram id1 is the only label which will appear.

   Control statement: fixed.

     id1 = fixed 0
     id2 = fixed -1

These lines mean that id1 is fixed at the left (or top) end of the cells structure, and id2 is fixed at the right (or bottom) end. While there is an intent to allow a general id fixed number format, that is currently not implemented.

   Control statement: end

    end

End must appear at the end of the text to be processed in a separate complete line. Everything after the end line will be ignored. 

EXAMPLE:

this example includes three non implemented line types, aoi, cut, and near. They have been commented out, since they do not work.

-----------------------------------------------------------------------

--aluslice.txt

aBus	= nor	[ a1 b1 c1 ]
a1  	= nor	[ (abus_ar)' ar' ]
ar'	= nor	[ ar ]
ar	= pass	[ arHold q1 ]
q1	= nor	[ s ]
s	= wire	[ s1 s2 ]
s1	= pass	[ ar_bus bus ]
s2	= pass	[ arHold r1 ]
r1	= nor	[ q1 ]
b1	= nor	[ (abus_a)' a' ]
a'	= nor	[ a ]
a	= pass	[ aHold q2 ]
q2	= nor	[ q2' ]
q2'	= wire	[ t1 t2 ]
t1	= pass	[ a_bus bus ]
t2	= pass	[ aHold r2 ]
r2	= nor	[ q2 ]
c1	= nor	[ (abus_pc)' pc' ]
cyOut	= nor	[ pc' cyIn' ]
cyIn'	= nor	[ cyIn ]
pc	= nor	[ pc' ]
pc'	= nor	[ pc2 ]
pc2	= pass	[ pcHold q3 ]
q3	= nor	[ u ]
u	= wire	[ u1 u2 u3 u4 ]
u1	= pass	[ pcLow_a a ]
u2	= pass	[ pcHold q3' ]
q3'	= nor	[ q3 ]
u3	= pass	[ pc_pc+1 m ]
m	= nor	[ pc' cyIn pc cyIn' ]
--m	= aoi	[ pc' cyIn pc cyIn' ]
u4	= pass	[ pc_stk n ]
n	= nor	[ n' ]
n'	= pass	[ stkHold v' ]
v'	= nor	[ v ]
v	= wire	[ v1 v2 v3 ]
v1	= pass	[ push m ]
v2	= pass	[ stkHold vx ]
vx	= nor	[ v' ]
v3	= pass	[ pop stk1 ]

--q3	= cut	u
--s	= cut	s2
--q2'	= cut	t2
--v	= cut	v2
bus	= fixed	-1
aBus	= fixed	0
--cyOut	= near	cyIn

end