Inter-Office MemorandumToTaft, Boggs, HuntDateMarch 30, 1978Strollo, StewartFromLarry StewartLocationPalo AltoSubjectAlto-1822 InterfaceOrganizationSSLMicrocode & Emulator InterfaceXEROX Filed on: [Maxc1]AISwSpec.pressAbstractThe Alto-1822 interface is now substantially working. This memo describes what is hoped to be thefinal interface specification. The bit patterns used to control it are unlikely to change again.Naturally, the emulator interface depends on the 1822 microcode. Included here is the microcodewritten for the 1822 test program, which may provide a plausible base for other situations.General NotesHardware:The Alto-1822 interface is a processor bus device requiring a single Task. It is designed to conformto the requirements of BBN Report 1822. As such it is suitable for Arpanet or Packet Radio Netuse. The interface is a full duplex device with no buffering beyond 16 bit input and output shiftregisters. 1822 specifies a bit-by-bit handshaking protocol intended to allow interconnection ofmachines with different word lengths - data transfer may pause for essentially arbitrary intervals (i.e.seconds) between any two bits.Performance:The input and output data transfer sections of the interface are controlled by PROM based finitestate machines clocked by the Alto at 170 ns intervals. With zero delays at the IMP end the inputand output sections can each transfer a bit every six cycles - just under 1 Megabit per second.Actual transfer rates will be somewhat less. In loopback mode the throughput is about 680 Kb/s.Hardware - Microcode InterfaceControl of the hardware is accomplished through the emulator SIO instruction and various TaskSpecific F1's and F2's. The SIO/wakeup/branch logic is controlled by a PROM based finite statemachine. Included here is a rather low level description of what the various functions and SIO'sdo. It is recommended that the reader look at the next section, describing the emulator interface ofthe test microcode before starting off to write his own!SIO functions:The interface task wakeup logic responds to bits 5 and 6 of the Bus during execution of an SIO(Task 0 STARTF):ЪН]Оg║pТjНІОc8qН]rТXН-єqН7Br Н]ОaЁНІО]ЭqН]rН-єqН7BrНІОYqН]rН-єqН7BrН]ОW│НЭОSЛsrНЇОMЪП)НЇОIrtНЇОF█rТ┌П;Т┐П'НЇОEТвПHurТь НЇОC┐Т≥ПJТ НЇОAЧТ─П[НЇО=qtТXНЇО9╦uНЇО6сrТ┘П1Т├П4НЇО5NТ≤Т≥ПLНЇО3иТ╔ПPТіНЇО2DТхП3ТиП.НЇО0©Т─Т│П[НЇО/:Т─НЇО+│uНЇО(°rТ╒ПSТёНЇО'Т▐ПLТ░НЇО%▓Т╪ПWТҐНЇО$ Т─П`НЇО─tТXНЇО⌡rТ╡П]НЇОТ≈П4Т≤П+НЇО▒Т╒П#ТёП>НЇОТ└Т┘ПaНЇО┤Т─П8НюОнu НюОИrТїП;Т╗П#НюОdТ─ЪtЭ=ГZЕЫAlto-1822 Interface, Software Interface2SIO #3000 sets wakeup and arranges for the IBRNCH function to put '01' on NEXT[6-7].In the attached microcode, this operation is used to start the 'Control' microcode.This wakeup is cleared by ISWAKCSIO #2000 sets wakeup and arranges for the IBRNCH function to put '00' on NEXT[6-7].In the attached microcode, this operation is used to start the 'Start Input' microcode.This wakeup is cleared by ISWAKCSIO #1000 enables the output hardware in such a way that wakeup is set and theIBRNCH function will put '10' on NEXT[6-7]. In the attached microcode, thisoperation is used to start an output data transfer. This wakeup is cleared by IOCLR.Task Specific Functions:IBRNCH (F2-13):Gates two bits from the Control PROM to NEXT[6-7].'00' - caused by SIO #2000 'Input Start''01' - caused by SIO #3000 'Control''10' - caused by output hardware data request and (indirectly) by SIO #1000 'Output Start''11' - caused by input hardware data availableISWAKC (F2-14):Clears wakeups generated by SIO #2000 and SIO #3000 onlyIPOSTF (F1-14):Gates hardware status to the Bus.Bit 15: IMP Relay WAS off, it may still be off.Bit 16: IMP Ready Relay is OPEN (off)Bit 17: Host Ready flipflop is OFF (and so is the relay)Other bits are left as 1's.ISETCS (F2-11):Decodes the Bus to set and clear various controls in the interface.#000000 - Does nothing#000001 - Master Reset. Clears all wakeups, turns off all data transfers, but does not affectthe relay.#000002 - Set Last Word. Used after an IWRITE, this will set the 'LastWord' flipflop,causing 'LastHostBit' to be transmitted at the end of the current data word.#000003 - Try Clearing ImpWasDown. If the Imp is now READY, this will clear the'Imp Was Down' status bit. Otherwise it won't.#000004 - Turn on Hardware LoopBack#000005 - Turn off Hardware LoopBack#000006 - Turn on Host Ready Relay#000007 - Turn off Host Ready Relay#002000 - Turn on Discard Flipflop (see IPTMOD)#001000 - Turn off Discard FlipflopOther bit patterns are undefined.IPTMOD (F2-10):Gates the 'Discard' flipflop to NEXT[7]. In the attached microcode this operation is usedduring Packet Discard Mode to dispatch to a different section of input data transfermicrocode.IOCLR (F1-15):НЇОfПrТ─П'НGОНґОbТ█ПAТ▌Н√О`≥Т╨П4Т╩Н√О_Т─НґО\/Т█ПAТ▌Н√ОZ╙Т▐ПWН√ОY%Т─НґОV@ТГПFТХН√ОT╩ТуП<ТжН√ОS6Т─ПUНюОO}uНюОL≤rНІОJ├П2НґОIП(НґОG|П$НґОEВПZНґОDrП.НюОA█НґО?5П4uНюОнrПdНЇО=IП(НЇО:dН2О7НёНН2О5ЗНёНН2О4uНёНП%НЇО1░Н2О.╚НґО-&НґО+║Н≥НП"НґО* Н≥ННґО(≈ Н≥ННґО'Н≥ННґО%█НЇО"╗uНЇОцrП]НЇО>П=НЇОYН2ОtН(Н2ООН(Н2ОjН(urНёОЕП$Н2О`Н(urНёОшП(Н2ОVН(П&НёО яП1Н2ОLН(юЇ=g\ЗAlto-1822 Interface, Software Interface56turn on Host Ready relay7turn off Host Ready relay2000turn on packet throwaway mode1000turn off packet throwaway modePacket Throwaway Mode:By executing an SIO-set control function, the user may set the receiver hardware into "PacketThrowaway Mode". On each SIO-start receiver call (until the throwaway mode is cleared), themicrocode will read in a packet (i.e. until the next Last Imp Bit) and throw it away. Although it isnot used, the input buffer must have some space in it.Zero buffer length:On output, there is no longer any initialization microcode - the SIO reaches down into the outputfinite state machine and makes it think it was running already. The FSM then requests a normaloutput data wakeup to get the first word. Thus if the buffer size is zero, on that first wakeup themicrocode will conclude that transmission is done and return normal end status - without havingdone anything. On input, while a zero length buffer probably represents a programming error, themicrocode will return a bad status. If the receiver were actually started with a zero size buffer, thecondition would not be noticed until the first input data wakeup. At that time, the microcodewould have no choice but to throw away the input word and return a buffer overflow error - theentire packet would be messed up. With the current microcode, you can request input into a zerolength buffer, get an error status back, and restart the operation with a non-zero buffer withoutlosing data.Microcode timingA copy of the newest microcode is attached. The code uses one S register. I include here a tableof timing information. A '+' indicates a TASK.OperationMicrocyclesEmulator control/status call15Emulator input request(Buffer length zero)17Emulator input request(Buffer length non-zero)12Emulator output request 0Input wakeup(Buffer Overflow)20Input wakeup(Normal)18Input wakeup(Last word)18+10(wierd kludge)Input wakeup(Normal throwaway)13Input wakeup(Last throwaway)13+10Output wakeup(Normal)18Output wakeup(Last word)18Output wakeup(Normal end)19ЪНЇОfПrТ─П'НGОН2ОbН(ТXu rН2О`≥Н(u rН2О_Н(Н2О]▐Н(НЇОYжuНЇОVЯrТиП-ТйП0НЇОUlТ╪П8ТҐП$НЇОSГТ┴П5urП!Т┼НЇОRbТ─П6НЇОN╘uТXНЇОKдrТ≤П!Т≥П@НЇОJ?Т⌡П'Т°П8НЇОH╨Т∙ПBТ√П"НЇОG5Т╗ Т╘ПQНЇОE╟Т▌П]Т▐НЇОD+Т▄П9Т█П.НЇОBіТ╨Т╩ПHНЇОA!Т²ПBТ·НЇО?°Т▒П"Т▓П>НЇО>Т╦ПIТ╧uНЇО<▓rТ─НЇО8LpТjНЇО4LrТ⌠П@Т■П"НЇО2гТ─П/НЇО/НЇО.жЧНкО/НкО.жЧгН ▓О/Н ▓О.жЧ╔Н7О/Н7О.жЧ└Н╩О/Н╩О.жЧ╔Н`О/Н`О.жЧoНоО/НоО.жЧcН2О/Н2О.жЧ╩НМО/НМО.жЧгНЄО.жЧ НюО.жЧ@Н2О/Н2О.жЧVН3VО/Н3VО.жЧcН3╧О/Н3╧О.жЧ⌡Н4TО/Н4TО.жЧ└Н4ьО/Н4ьО.жЧ╩Н5⌠О/Н5⌠О.жЧ⌡Н6.О/Н6.О.жЧ╟Н6чО/Н6чО.жЧ⌡Н7yО/Н7yО.жЧcН7эО/Н7эО.жЧ╔Н8│О/Н8│О.жЧ└НЇО+UТXН2НЇО)пН `vТGН2rНЇО(KТXН `vТGН2rНЇО&фТXН `НЇО%AН `vТGН2rНЇО#╪ТXН `vН2rНЇО"7Н `vТG Н2rН=Sv НЇО ╡rТXН `vТG Н2rНЇО-ТXН `vТG Н2rНЇО╗ТXН `vН2rНЇО#Н `vТG Н2rНЇО·ТXН `vТGН2r$ЇW=gMЁЩAlto-1822 Interface, Software Interface6Microcode; Larry Stewart March 25, 1978 11:37 PM#AltoConsts23.mu;; Address definition for Emulator main loop in ROM$START $L004020,000000,000000 ; Start of emulator main loop; Task Specific Function Definitions$IREAD $L000000,070017,000100 ; F1-17Input data$IWRITE$L020016,000000,124000 ; F1-16Output data$IOCLR $L016015,000000,000000 ; F1-15Clear hardware output wakeup$IPOSTF$L016014,066014,000100 ; F1-14Post (gate status to bus)$ISWAKC$L024014,000000,000000 ; F2-14Clear SIO generated wakeup$IBRNCH$L024013,000000,000000 ; F2-134-way branch on wakeup$IIENBL$L024012,000000,000000 ; F2-12Start read (turn on RFNIB)$ISETCS$L024011,000000,000000 ; F2-11Set control functions from bus$IPTMOD$L024010,000000,000000 ; F2-102-way branch on throwaway mode;R (S) registers$ICBPTR$R76;Control Block Pointer$MTEMP $R25;Temporary storage$AC1 $R2;Emulator register$NWW $R4;Interrupt system reg; Task constants$ISDON $777;done$ISOVF $1377;buffer overflow (input only)$ISIBLZ$1777;block length zero (input only); Initialization for putting this code in the RAM, including ; 'silent boot' code!17,20,LOC0,IMLOOP,,,,,,,,,,,,,,;;Silent Boot code, branches to ROM immediatelyLOC0:SWMODE;:START;;Main loop. Task waits here when not processing anything.;IBRNCH gates two bits onto NEXT6 and NEXT7 ; 00 - Start input 01 - Set Control ; 10 - Output data wakup 10 - Input data wakeup; 4-way branch using NEXT6,NEXT7 (Caused by IBRNCH)%14,14,0,IISTRT,ICTST,IODATA,IIDATA;IMLOOP:T_ ICBPTR,IBRNCH;test wakeup conditionsL_ ISDON,:IISTRT;[IISTRT,ICTST,IODATA,IIDATA];Common Post routine ; Expects offset of post location in TНЇОfПrТ─П'НGОНЇОaвpНЇО^мwТьП(НЇО[цНЇОX╧П2НЇОU╞П;НЇОR╔П$НЇОO⌡П%Н.Ї НЇОNП%Н.Ї НЇОL▒П%Н.ЇНЇОKП%Н.ЇНЇОI┤П%Н.ЇНЇОHП%Н.ЇНЇОF}П%Н.ЇНЇОDЬП%Н.ЇНЇОCsП%Н.ЇНЇО@iНЇО=_Н.ЇНЇО;зН.ЇНЇО:U Н.ЇНЇО8п Н.ЇНЇО5фНЇО2╪Н.ЇНЇО17Н.ЇНЇО/╡Н.ЇНЇО,╗П<НЇО+#НЇО)·xwНЇО&■П.НЇО%НЎНЎО#┼НЇО ─xП:НЇОvwП+НЇОЯП+НЇОlП7НЇОbП3НЇОщxwП#НЇОсxwНЎН.ЇНЎОNН.ЇНЇОDxНЇО©wП*┌ЇxНЇО#яП3НЇО"LНЇО гПBНЇОBПCНЇОҐП!НЇОЁП+НЇО.xwНЇО$П-НЇО÷xwНЇО∙П,НЇОxwНЇО П4ЮЇ©8┤[KАAlto-1822 Interface, Software Interface8%4,4,0,IIFINS,IIDPST;IIDATA:MAR_ L_ 2+T;Start fetchMTEMP_ L,IPTMOD;save cb ptr,test modeT_ MD;get pointer [IIACPT,IIDISC]IIACPT:L_ MD-T;past end of buffer?MAR_ T,SH=0;start data fetchL_ ONE+T,:IIDMOR;[IIDMOR,IIDFUL]IIDMOR:MD_ IREAD;Read and branch on last word. ;Except on the last word, this ;clears the wakeupIICLNU:MAR_ MTEMP,:IIDCON;[IIDCON,IIDLST]IIDCON:IIENBL,TASK;enable receiverIDCON:MD_ M,:IMLOOP;update ptr,restartIIDLST:TASK;this TASK only works ;because the hardware doesn't really clear the ;wakeup until the next IREAD in this caseMD_ M;update pointerL_ ISDON;IIDPST:SINK_ IREAD;clear wakeup (again)IIFINS:T_ 10,:IPOST;IIDISC:L_ T, T_ IREAD,:IICLNU;throwaway word,branch if lastIIDFUL:SINK_ IREAD;overflow statusL_ ISOVF,:IIFINS;[IIFINS,IIDPST];Main output loop;IWRITE loads the output shift register from the bus, ; clears the (hardware generated) wakeup if there was one, ; and starts the output hardware;IOCLR resets the output hardware. This is how you clear the ; wakeups without restarting the output hardware; 2-way branches using NEXT9 (both caused by SH=0)!1,2,IODMOR,IODEND;!1,2,IONLST,IOLST;IODATA:MAR_ L_ 4+T;start pointer fetchMTEMP_ L;save cb ptrT_ MD,IOCLR;get pointer, clear wakeupL_ MD-T;past end of buffer?MAR_ T,SH=0;start data fetchL_ M-1,:IODMOR;[IODMOR,IODEND]IODMOR:IWRITE_ MD,SH=0;send data,last?MAR_ MTEMP,:IONLST;start update [IONLST,IOLST]IOLST:SINK_ 2,ISETCS;set last word functionIONLST:L_ ONE+T,TASK,:IDCON;finishIODEND:T_ 11+1,:INEND;offset of post locЪНЇОfПrТ─П'НGОНЇОbxwНЇО_xwНЎТьН.Ї НЎО]▐Н.ЇНЎО\ Н.ЇНЇОZ┘НЎН.ЇНЎОYН.ЇНЎОW{Н.ЇНЇОTqНЎ Н.ЇНЇОRЛНЎНЇОQgНЎНЇОOБНЎН.ЇНЇОLьНЎН.ЇНЇОKSНЎ Н.ЇНЇОHIНЎН.ЇНЇОFдНЎП-НЇОE?НЎywНЎОB5Н.Ї НЎО@╟НЇО?+НЎН.ЇНЇО=іНЎНЇО:°НЎН.ЇНЇО7▓НЎН.ЇНЎО6 Н.ЇНЇО3xНЇО/ЫwП5НЇО.tП?НЇО,ОП%НЇО)ЕП=НЇО(`П6НЇО%VП2НЇО#яxwНЇО"LxwНЇОBxwНЎН.ЇНЎОҐН.Ї НЎО8Н.ЇНЎОЁН.ЇНЎО.Н.ЇНЎО╘Н.ЇНЇО÷НЎН.ЇНЎОН.ЇНЇО∙НЎН.ЇНЇОНЎН.ЇНЇО НЎН.ЇЇ:;w\п TIMESROMAN TIMESROMAN TIMESROMAN LOGO TIMESROMAN TIMESROMAN HELVETICAGACHA GACHA GACHA Й$#'Х-ЪЪj/0 .⌠0чЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪ aiswspec.memoStewartUnknown