{File name <tajo>dlBusExt.mc	for dlion assembly for dbBusExt.eb
Description: Daybreak Interlisp Emulator Bus Extension

use daybreak assembler on dbBusExt.mc to make dbBusExt.si and dbBusExt.ml
use dlion assembler on dlBusExt.mc to make dlBusExt.eb and rename to dbBusExt

Purcell  27-Jul-85 17:12:19 try memory timing
Purcell  27-Jul-85 13:17:53 edited
Purcell  22-Jul-85 22:50:49 created from BusExt.mc of 17-Apr-85  1:34:04 PST
}

{INPUT:	TOSH ← smallpl, DISP4[MiscIn],	c1, at[0D,10, MiscDisp];}

{
(SETQ MBUS.OUTL (PLUS 0 (LLSH REG 4)))
(SETQ MBUS.OUTM (PLUS 11 (LLSH REG 4)))
(SETQ MBUS.INL (PLUS 9 (LLSH REG 4)))
(SETQ MBUS.INM (PLUS 10 (LLSH REG 4)))

(\DEVICE.OUTPUT DATA MBUS.OUTL)
(\DEVICE.OUTPUT DATA MBUS.OUTM)
(SETQ DATA (\DEVICE.INPUT MBUS.INL))
(SETQ DATA (\DEVICE.INPUT MBUS.INM))
}
RegDef[uDummy,	UY,	0];	
RegDef[uDat,	U,	0D];{uTOS}{~0D = mBusStat or mBusIData}

{OpTable: , c1, at[500];}
		
BusX:	Noop,						c2, at[09,10,MiscIn];{read L}
	TOS ← TOS LRot12, 				c3;
	Ybus ← ~TOS, AltUaddr,				c1;
	Float.L, {TOS ← FloatResult}FloatA← uDummy,	c2;
pcInDn:	TOS ← FloatA← FloatResult, 			c3;

	GOTO[IB.nop],					c1;

	Noop,						c2, at[0A,10,MiscIn];{read M}
	TOS ← TOS LRot12, 				c3;
	Ybus ← ~TOS, AltUaddr,				c1;
	Float.M, {FloatResult}FloatA← uDummy,GOTO[pcInDn], c2;


	Noop,						c3, at[0,10,MiscOut];{Write L}	
	Rx ← S + 2,					c1;
	Q ← rhS, 					c2;
	rhRx ← Q LRot0, 				c3;
			
	MAR ← Rx ← [rhRx, Rx + 0],			c1;
	TOS ← TOS LRot12,				c2;
	TT ← MD,					c3;
	
	uDat ← TT,					c1;
	Ybus ← ~TOS, AltUaddr, L2 ← L2.0, IBDisp,	c2;
	Float.L, Xbus ← uDat, L2 ← L2.0, DISPNI[OpTable], c3;


label:	Noop,						c3, at[0B,10,MiscOut];{Write M}	
	Rx ← S + 2,					c1;
	Q ← rhS,					c2;
	rhRx ← Q LRot0,					c3;
	
	MAR ← Rx ← [rhRx, Rx + 0],			c1;
	TOS ← TOS LRot12,				c2;
	TT ← MD,					c3;
	
	MAR ← Rx ← [rhRx, Rx + 0],{uDat ← TT,}		c1;
	Ybus ← ~TOS, AltUaddr, L2 ← L2.0, IBDisp,	c2;
	Float.M, Xbus ← MD{uDat}, L2 ← L2.0, DISPNI[OpTable], c3;

	{ E N D }