{File name: <Workstation>mc>Misc.mc
Description: Miscellaneous Mesa opcodes,
Author: R. Garner,
Created: April 3, 1980,
Last Edited: Amy Fasnacht, 31-Aug-83 10:50:05 Move IOPage for larger VM
Last Edited: Daniels, 15-Jun-83 19:01:49 new instruction set
Last Edited: Amy Fasnacht, 4-Jan-83 10:52:30 Fix typo in BLTLR comment
Last Edited: Amy Fasnacht, 22-Dec-82 10:49:15 Make BLTLR microcode implementation
Last Edited: Amy Fasnacht, September 2, 1982 12:19 PM Do STK←TOS at Unimplemented Opcodes
Last Edited: Amy Fasnacht, August 2, 1982 11:41 AM MaintenancePanelOffset
Last Edited: Amy Fasnacht, April 29, 1982 1:48 PM Add TStatus to @INPUT and TAddr to @OUTPUT
Last Edited: Amy Fasnacht, April 23, 1982 2:01 PM Add conditional assembly for MagTape
Edited: Sandman, February 24, 1982 2:18 PM Add SPP inst
Edited: Sandman, November 17, 1981 5:04 PM new instruction set
Edited: Sandman, April 23, 1981 8:46 AM: Fix Stack on Misc ~IN[0..15]
Last Edited: Jim Frandeen, March 16, 1981 11:51 AM: Allow Block to catch Checksum Misc
Last Edited: Johnsson, January 22, 1981 1:11 PM}
{Assembly Configs:
Config# File
0 Mesa.db
1 RavenMesa.db
2 TridentMesa.db
3 TridentRavenMesa.db
4 MagTapeMesa.db
5 TridentMagTapeMesa.db}
{*****************************************************************************
ESC(L) - Escape operations
*****************************************************************************}
@ESCL: Xbus ← ibHigh, XDisp, GOTO[ESCx], c1, opcode[371'b];
@ESC: Xbus ← ibHigh, XDisp, c1, opcode[370'b];
ESCx: TT ← ib, XDisp, push, DISP4[ESCHi], c2;
PC ← PC + 1, STK ← TOS, pop, DISP4[ESC0n], c3, at[0,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, DISP4[ESC1n], c3, at[1,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, DISP4[ESC2n], c3, at[2,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[3,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[4,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[5,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[6,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, DISP4[ESC7n], c3, at[7,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, DISP4[ESC8n], c3, at[8,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[9,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0A,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0B,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0C,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0D,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0E,10,ESCHi];
PC ← PC + 1, STK ← TOS, pop, CANCELBR[ESCa,0F], c3, at[0F,10,ESCHi];
ESCa: PC ← PC - 1, c1;
ESCb: T ← 0FF + TT + 1, c2;
ESCc: G ← 1, GOTO[Trapc1], c3;
ESC0n: PC ← PC - 1, GOTO[ESCb], c1, at[0,10,ESC0n];
PC ← PC - 1, GOTO[ESCb], c1, at[1,10,ESC0n];
{@MW in Process c1, at[2,10,ESC0n];}
{@MR in Process c1, at[3,10,ESC0n];}
{@NC in Process c1, at[4,10,ESC0n];}
{@BC in Process c1, at[5,10,ESC0n];}
{@REQ in Process c1, at[6,10,ESC0n];}
{@SM in Misc c1, at[7,10,ESC0n];}
{@SMF in Misc c1, at[8,10,ESC0n];}
{@GMF in Misc c1, at[9,10,ESC0n];}
{@AF in Xfer c1, at[0A,10,ESC0n];}
{@FF in Xfer c1, at[0B,10,ESC0n];}
{@PI in Xfer c1, at[0C,10,ESC0n];}
{@PO in Xfer c1, at[0D,10,ESC0n];}
{@POR in Xfer c1, at[0E,10,ESC0n];}
{@SPP in Process c1, at[0F,10,ESC0n];}
{@DI in Xfer c1, at[0,10,ESC1n];}
{@EI in Xfer c1, at[1,10,ESC1n];}
{@XOR in Stack c1, at[2,10,ESC1n];}
{@DAND in Stack c1, at[3,10,ESC1n];}
{@DIOR in Stack c1, at[4,10,ESC1n];}
{@DXOR in Stack c1, at[5,10,ESC1n];}
{@ROTATE in Stack c1, at[6,10,ESC1n];}
{@DSHIFT in Stack c1, at[7,10,ESC1n];}
{@LINT in Stack c1, at[8,10,ESC1n];}
{@JS in Jump c1, at[9,10,ESC1n];}
{@RCFS in StringField c1, at[0A,10,ESC1n];}
{@RC in Read c1, at[0B,10,ESC1n];}
{@UDIV in Stack c1, at[0C,10,ESC1n];}
{@LUDIV in Stack c1, at[0D,10,ESC1n];}
{@ROB in Read c1, at[0E,10,ESC1n];}
{@WOB in Write c1, at[0F,10,ESC1n];}
{@DSK in Xfer c1, at[0,10,ESC2n];}
{@XE in Xfer c1, at[1,10,ESC2n];}
{@XF in Xfer c1, at[2,10,ESC2n];}
{@LSK in Xfer c1, at[3,10,ESC2n];}
{@BNDCKL in Stack c1, at[4,10,ESC2n];}
{@NILCK in Stack c1, at[5,10,ESC2n];}
{@NILCKL in Stack c1, at[6,10,ESC2n];}
{@BLTLR in Block c1, at[7,10,ESC2n];}
{@BLEL in Block c1, at[8,10,ESC2n];}
{@BLECL in Block c1, at[9,10,ESC2n];}
{@CKSUM in Block c1, at[0A,10,ESC2n];}
{@BITBLT in BBInit c1, at[0B,10,ESC2n];}
IfEqual[Config, 0, SkipTo[TextBltImpl], ];
@TXTBLT:
PC ← PC - 1, GOTO[ESCb], c1, at[0C,10,ESC2n];
TextBltImpl!
@BYTBLT:
PC ← PC - 1, GOTO[ESCb], c1, at[0D,10,ESC2n];
@BYTBLTR:
PC ← PC - 1, GOTO[ESCb], c1, at[0E,10,ESC2n];
@VERSION:
PC ← PC - 1, GOTO[ESCb], c1, at[0F,10,ESC2n];
@a177: PC ← PC - 1, GOTO[ESCb], c1, at[0F,10,ESC7n];
{@INPUT in Misc c1, at[0,10,ESC8n];}
{@OUTPUT in Misc c1, at[1,10,ESC8n];}
@LOADRAMJ:
PC ← PC - 1, GOTO[ESCb], c1, at[2,10,ESC8n];
IfEqual[Config, 1, SkipTo[BandBltImpl], ];
IfEqual[Config, 3, SkipTo[BandBltImpl], ];
@BANDBLT:
PC ← PC - 1, GOTO[ESCb], c1, at[3,10,ESC8n];
BandBltImpl!
PC ← PC - 1, GOTO[ESCb], c1, at[4,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[5,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[6,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[7,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[8,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[9,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0A,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0B,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0C,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0D,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0E,10,ESC8n];
PC ← PC - 1, GOTO[ESCb], c1, at[0F,10,ESC8n];
{*****************************************************************************
SM Set Map
*****************************************************************************}
@SM: TOS ← TOS and 7, pop, c1, at[7,10,ESC0n];
TT ← STK, pop, c2;
TT ← TT LRot8, c3;
Xbus ← STK, pop, c1;
T ← STK, pop, c2;
rhT ← T ← T LRot8, c3;
TOS ← TOS LRot4, fXpop, push, c1;
TT ← TT and ~0F0, c2;
TT ← TT or TOS, Xbus ← TOS LRot12, XDisp, c3;
SMd: Map ← [rhT,T], T ← 80, DISP4[SMc,8], c1;
SMc: MDR ← TT and ~T, IBDisp, GOTO[SLa], c2, at[08,10,SMc];
MDR ← TT and ~T, IBDisp, GOTO[SLa], c2, at[09,10,SMc];
MDR ← TT or T, IBDisp, GOTO[SLa], c2, at[0A,10,SMc];
MDR ← TT or T, IBDisp, GOTO[SLa], c2, at[0B,10,SMc];
MDR ← TT and ~T, IBDisp, GOTO[SLa], c2, at[0C,10,SMc];
MDR ← TT and ~T, IBDisp, GOTO[SLa], c2, at[0D,10,SMc];
MDR ← TT and ~T, IBDisp, GOTO[SLa], c2, at[0E,10,SMc];
MDR ← TT or T, IBDisp, GOTO[SLa], c2, at[0F,10,SMc];
{*****************************************************************************
SMF Set Map Flags
*****************************************************************************}
@SMF: pop, L0←0, c1, at[8,10,ESC0n];
T ← STK, pop, c2;
SMFa: TOS ← TOS and 7, fXpop, push, c3;
rhT ← T ← T LRot8, c1;
Rx ← ~80, c2;
TT ← TOS{map flags} LRot4, c3;
Map ← [rhT,T], c1;
Q ← ~0F0, c2;
TOS ← Rx and MD, c3;
Rx ← TOS LRot12, XDisp{disp old flags}, c1;
TOS ← TOS and Q, DISP4[SMFb,8], c2;
SMFb: TT ← TOS or TT, GOTO[SMFc], c3, at[08,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[09,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[0A,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[0B,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[0C,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[0D,10,SMFb];
TT ← TOS or 60, GOTO[SMFc], c3, at[0E,10,SMFb];
TT ← TOS or TT, GOTO[SMFc], c3, at[0F,10,SMFb];
SMFc: Rx ← Rx and 7, c1;
TOS ← TOS LRot8, push, c2;
STK ← Rx, push, L0Disp, c3;
STK ← TOS, push,BRANCH[SMFd, GMFa], c1;
SMFd: STK ← 0, c2;
Xbus ← TT LRot12, XDisp, GOTO[SMd], c3;
{*****************************************************************************
GMF Get Map Flags
*****************************************************************************}
@GMF: T ← STK, pop, L0←1, c1, at[9,10,ESC0n];
GOTO[SMFa], c2;
GMFa: STK ← 0, IBDisp, GOTO[SLa], c2;
{*****************************************************************************
INPUT Input
*****************************************************************************}
@INPUT: Ybus ← TOS, YDisp, c1, at[0,10,ESC8n];
fXpop, push, IBDisp, DISP4[Input], c2;
Input: TOS ← EIData, DISPNI[OpTable], c3, at[0,10,Input];
TOS ← EStatus, DISPNI[OpTable], c3, at[1,10,Input];
TOS ← KIData, DISPNI[OpTable], c3, at[2,10,Input];
TOS ← KStatus, DISPNI[OpTable], c3, at[3,10,Input];
TOS ← MStatus, DISPNI[OpTable], c3, at[5,10,Input];
TOS ← KTest, DISPNI[OpTable], c3, at[6,10,Input];
TOS ← IOPIData, DISPNI[OpTable], c3, at[8,10,Input];
TOS ← IOPStatus, DISPNI[OpTable], c3, at[9,10,Input];
TOS ← TStatus, DISPNI[OpTable], c3, at[0A,10,Input];
{*****************************************************************************
OUTPUT Output
*****************************************************************************}
@OUTPUT:
T ← STK, pop, Ybus ← TOS, YDisp, c1, at[1,10,ESC8n];
TOS ← STK, pop, IBDisp, DISP4[Output], c2;
Output: IOPOData ← T LRot0, DISPNI[OpTable], c3, at[0,10,Output];
IOPCtl ← T LRot0, DISPNI[OpTable], c3, at[1,10,Output];
KOData ← T LRot0, DISPNI[OpTable], c3, at[2,10,Output];
KCtl ← T LRot0, DISPNI[OpTable], c3, at[3,10,Output];
EOData ← T LRot0, DISPNI[OpTable], c3, at[4,10,Output];
EICtl ← T LRot0, DISPNI[OpTable], c3, at[5,10,Output];
PCtl ← T LRot0, DISPNI[OpTable], c3, at[9,10,Output];
MCtl ← T, DISPNI[OpTable], c3, at[0A,10,Output];
EOCtl ← T LRot0, DISPNI[OpTable], c3, at[0C,10,Output];
KCmd ← T LRot0, DISPNI[OpTable], c3, at[0D,10,Output];
TAddr ← T LRot0, DISPNI[OpTable], c3, at[0E,10,Output];
POData ← T LRot0, DISPNI[OpTable], c3, at[0F,10,Output];
{*****************************************************************************
WR - Write Registers
*****************************************************************************}
@WRPSB: uPSB ← TOS, c1, at[0,10,ESC7n];
WRx: TOS ← STK, pop, IBDisp, GOTO[DISPNIonly], c2;
@WRMDS: UvMDS ← TOS, L0 ← 0, c1, at[1,10,ESC7n];
Q ← UvL, c2;
WRMDSc: rhMDS ← UvMDS, c3;
Map ← Q ← [rhMDS, Q], L0Disp, c1;
BRANCH[WRMDSa, WRMDSb], c2;
WRMDSa: L ← rhL ← MD, c3;
MAR ← L ← [rhL, Q+0], c1;
Q ← UvG, L0 ← 1, GOTO[WRMDSc], c2;
WRMDSb: G ← rhG ← MD, c3;
MAR ← G ← [rhG, Q+0], GOTO[WRx], c1;
@WRWP: uWP ← TOS, GOTO[WRx], c1, at[2,10,ESC7n];
@WRWDC: uWDC ← TOS, GOTO[WRx], c1, at[3,10,ESC7n];
@WRPTC: uPTC ← TOS, GOTO[WRx], c1, at[4,10,ESC7n];
@WRIT: T ← STK, pop, c1, at[5,10,ESC7n];
TT ← TOS, c2;
TOS ← STK, pop, c3;
{must write all three clock regs in single click}
uClockHigh ← TT, c1;
uClockLow ← T, IBDisp, c2;
uClockBits ← 0, DISPNI[OpTable], c3;
@WRXTS: uXTS ← TOS, GOTO[WRx], c1, at[6,10,ESC7n];
@WRMP: Rx ← uIOPage, c1, at[7,10,ESC7n];
Q ← MaintenancePanelOffset, c2;
rhRx ← IOPageHigh, c3;
MAR ← [rhRx, Q + 0], c1;
MDR ← TOS, IBDisp, GOTO[SLa], c2;
{*****************************************************************************
RR - Read Registers
*****************************************************************************}
@RRPSB: TOS ← uPSB, push, GOTO[RRx], c1, at[8,10,ESC7n];
RRx: push, fZpop, IBDisp, GOTO[DISPNIonly], c2;
@RRMDS: TOS ← UvMDS, push, GOTO[RRx], c1, at[9,10,ESC7n];
@RRWP: TOS ← uWP, push, GOTO[RRx], c1, at[0A,10,ESC7n];
@RRWDC: TOS ← uWDC, push, GOTO[RRx], c1, at[0B,10,ESC7n];
@RRPTC: TOS ← uPTC, push, GOTO[RRx], c1, at[0C,10,ESC7n];
@RRXTS: TOS ← uXTS, push, GOTO[RRx], c1, at[0E,10,ESC7n];
@RRIT: Q ← uClockHigh, push, c1, at[0D,10,ESC7n];
TOS ← RShift1 uClockBits, SE←0, c2;
TT ← uClockLow, push, GOTO[ADCa], c3;
{*****************************************************************************
Unimplemented Opcodes
*****************************************************************************}
Unimp: TT ← 76'b, push, GOTO[OpcodeTrap], c1, opcode[76'b];
TT ← 77'b, push, GOTO[OpcodeTrap], c1, opcode[77'b];
TT ← 175'b, push, GOTO[OpcodeTrap], c1, opcode[175'b];
TT ← 176'b, push, GOTO[OpcodeTrap], c1, opcode[176'b];
TT ← 177'b, push, GOTO[OpcodeTrap], c1, opcode[177'b];
TT ← 277'b, push, GOTO[OpcodeTrap], c1, opcode[277'b];
TT ← 372'b, push, GOTO[OpcodeTrap], c1, opcode[372'b];
TT ← 373'b, push, GOTO[OpcodeTrap], c1, opcode[373'b];
TT ← 374'b, push, GOTO[OpcodeTrap], c1, opcode[374'b];
TT ← 375'b, push, GOTO[OpcodeTrap], c1, opcode[375'b];
TT ← 376'b, push, GOTO[OpcodeTrap], c1, opcode[376'b];
OpcodeTrap:
T ← sOpcodeTrap, STK ← TOS, pop, GOTO[ESCc], c2;
{ E N D }