0_(* * This is a hand edited example of a BusMaster.TestScript)
*
1_(DRIBBLE '{ERIS}<LispCore>BUSMASTER>BUSMASTER.TESTLOG)
NIL
2_(MAKESYSDATE)
10-Oct-85 18:23:43
3_(* * Files haven't been moved from LispCore yet)
*
4_(PUSH DIRECTORIES '{ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2]
(DIRECTORIES reset)
({ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2 {ERIS}<LISP>KOTO>LIBRARY> 
{ERIS}<LISP>KOTO>LISPUSERS> {ERIS}<LISPUSERS> {ERIS}<LISP>KOTO>SOURCES> 
{PHYLUM}<LISP>KOTO>LIBRARY> {PHYLUM}<LISP>KOTO>LISPUSERS> {PHYLUM}<LISPUSERS> 
{PHYLUM}<LISP>KOTO>SOURCES>)
5_FILESLOAD[BUSMASTER]

{ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>BUSMASTER.DCOM;1
compiled on 28-Sep-85 17:38:51
FILE CREATED 16-Sep-85 14:43:58
BUSMASTERCOMS

{ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>BUSEXTENDER.DCOM;1
compiled on 28-Sep-85 17:35:49
FILE CREATED 19-Aug-85 11:14:06
BUSEXTENDERCOMS
({ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>BUSMASTER.DCOM;1)
6_(PC.CHECKOUT)
Status loopback OK
8-bit data loopback OK
16-bit data loopback OK
DMA loopback OK
Receiver data register loopback OK
Receiver address registers loopback OK
Memory there OK - page numbers 1
T
7_(FILESLOAD PCMEMTEST TOGMENU)

{ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>PCMEMTEST.DCOM;4
compiled on 29-Sep-85 18:50:11
FILE CREATED 29-Sep-85 18:11:53
PCMEMTESTCOMS

{ERIS}<LISP>KOTO>LISPUSERS>TOGMENU.DCOM;1
compiled on 12-Apr-85 17:14:11
FILE CREATED 12-Apr-85 17:13:45
TOGMENUCOMS
({ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>PCMEMTEST.DCOM;4
{ERIS}<LISP>KOTO>LISPUSERS>TOGMENU.DCOM;1)
8_(PCMEM.CHECKOUT)
There is memory on the PC at page address(es) 1.
Memory refresh DMA OK
Running in ELT in QuietTestBltIn in PCMEM.CHECKOUT
.....+
9_(PCMEM.MAKETEST]
{WINDOW}#74,30404
10_(* Use middle button in menus to change parameters:
Summarize every: 1
# passes: 300
Size of Block 10000
Direction: FastIn
Pattern: rand
left button: START)
(* read: "Pattern stored, XXX errors (ignore)................
0 read errors
0 memory decays
0 slow faults)
11_(* * Remove BusMaster cable from CPE processor card)
*
12_(PC.CHECKOUT)
Status loopback failure: test:0 a16:0 a8:0 a0:0 in,
                         test:1 a16:0 a8:1 a0:0 out.
There is some indication that the failure indicated above results from the 
fact that either the busmaster is powered down, or there isn't anything 
connected to the parallel I/O port where the busmaster should be - please 
check that the busmaster is indeed cabled up to the bottom socket on the CPE 
(3) board of the Dandetiger and that it has power.
NIL
13_(* * Reconnect BusMaster cable to CPE)
*
14_(* * Switch OFF expansion chassis power)
*
15_(PC.CHECKOUT)
Status loopback OK
8-bit data loopback failure: 40 in,
                              0 out.
NIL
16_(* * Switch ON expansion chassis power)
*
17_(PC.CHECKOUT)
Status loopback OK
8-bit data loopback OK
16-bit data loopback OK
DMA loopback OK
Receiver data register loopback OK
Receiver address registers loopback OK
Memory there OK - page numbers 1
T
18_FILESLOAD[PCDAC]

{ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>PCDAC.DCOM;1
compiled on 28-Sep-85 17:51:24
FILE CREATED 18-Sep-85 11:06:25
PCDACCOMS
({ERIS}<LISPCORE>BUSMASTER>KOTO>TEST2>PCDAC.DCOM;1)
19_PCDAC.MAKETEST]
{WINDOW}#65,160404
20_(* * set Sample Rate: 10K)
*
21_(* * set Display Every: AFAP)
*
22_(* * middle button in PC D/A-A/D Test Window: SCOPE)
*
23_(* * live oscilliscope is verified to work)
*
24_(* STOP key)
STOP
25_(DRIBBLE)