BUSTEST - a checkout tool for BusMaster cards Henry Thompson Initially released: 18 September 1985 File: {LOGOS:}DSL>BUSTEST.TEDIT This package is meant for debugging BusMaster cards and their initial connections to an external bus. As such it is meant for wizards with a detailed knowledge of that configuration. It contains a single function of interest , BUS.MAKETEST(). When called it produces a window with an associated command menu and 6 parameter TogMenus. [See the documentation of the TOGMENU Lispusers package for a complete discussion - in brief, a TogMenu shows its value, can be sequenced through a sequence of values with the left mouse button, and will bring up a standard menu, perhaps including some options not in the basic sequence, in response to the middle mouse button.] The available commands allow issuing memory read (MemRead) and write (MemWrite) commands and i/o port read (PortRead) and write (PortWrite) commands to the external bus connected to an 1108 with the Extended Processor option (the so-called 'DandyTiger'). The current version assumes this external bus is an IBM PC bus. Combinations of command sequences are also available: memory write followed by read (MemW/R), i/o port write followed by read (PortW/R) and memory write followed by port read (MW/PR). The menus which determine the parameter settings for the above operations are as follows: High Address The high order 4 bits of the 20 bit address for memory operations, in hexidecimal. Values provided are 1 and F, and others may be typed in (in hex). Low Address The low order 16 bits of the 20 bit address for memory operations, in hexidecimal. Values provided are 0, and others may be typed in (in hex). Port Address The port address for i/o port operations, in hexidecimal. Values provided are 0, data, HiAddr and LoAddr, and others may be typed in (in hex). data, HiAddr and LoAddr stand for the addresses of the data register (214 hex), high order address byte register (215 hex) and low order address byte register (216 hex) on the PC bus receiver card. Following memory write operations to non-existent pages (e.g. page F, usually), these address register should contain the high and low order bytes of the Low Address which was written to. Datum The byte to write in write operations. Values provided are 0 and FF, and others may be typed in (in hex). Quiet If No will display an indication of what operation was performed, and in the case of read operations, the value read. If Yes then no display is done. Loop If No then each click in the command menu produces a single operation. If Yes then the command selected will be performed in a tight loop until either a hard interrupt occurs or the STOP key is held down. Setting Quiet and Loop both to Yes provides a convenient source of stable repeated events for debugging with an oscilloscope or logic analyser. ** HELVETICA HELVETICA HELVETICA HELVETICA HELVETICA "&+š2 $*[˜’m™aU2z¹