{ File: [Idun]<WDLion>SysDefs.asm
Modification History:
Last modified by Jim Frandeen July 29, 1982 4:32 PM: Add Keyset
Last modified by Jim Frandeen May 24, 1982 10:30 AM rewrite
Created by Roy Ogus (July 9, 1979 4:21 PM)
}
; 8085 Interrupt mask definitions
InterruptEnbMsk equ 8 ; 1 => interrupts enabled (RIM)
Rst75DisableMsk equ 4 ; 1 => RST 7.5 disabled
Rst65DisableMsk equ 2 ; 1 => RST 6.5 disabled
Rst55DisableMsk equ 1 ; 1 => RST 5.5 disabled
MskSetEnable equ 8 ; 1 => interrupt masks being set (SIM)
ResetRst75 equ 10H ; 1 => reset restart 7.5's flip-flop
RSTMask equ Rst55DisableMsk+Rst65DisableMsk+Rst75DisableMsk
;SetIntrMask equ MskSetEnable+ResetRst75
; I/O Addresses.
; AltoPPI Defs
AltoPPI equ 80H ; Bank 0a
AltoPPIA equ AltoPPI+0 ; Port A
AltoPPIB equ AltoPPI+1 ; Port B
AltoPPIC equ AltoPPI+2 ; Port C
AltoPPICtrl equ AltoPPI+3 ; PPI Control
AltoPPImode equ 0BCH ; Port A, mode 1 input, B, mode 1, output, C[6:7] in
AltoPPImode0 equ 099H ; Port A, mode 0 input, B, mode 0, output, C in
EnableIntA equ 9H ; Enable interrupt A in PPI
EnableIntB equ 5H ; Enable interrupt B in PPI
IntAMask equ 8H ; Port A interrupt bit (Set PC4)
IntBMask equ 1H ; Port B interrupt bit (Set PC2)
; DMA Controller
{TC Stop and Extended Write bits. TC Stop causes the channel to be disabled after the Terminal Count goes true. Extended Write allows the DMA to wait for devices that are not fast enough to keep up with it.}
DmaModeExtra equ 60H ; TCS and EW bits in DmaMode
DmaTestReg equ 0D0H ; Test register for channel 2 (temp)
DmaBase equ 0A0H ; Bank 2
DmaCh0Addr equ DmaBase+0 ; Dma Channel-0 address (Floppy)
DmaCh0Count equ DmaBase+1 ; Dma Channel-0 count
DmaCh1Addr equ DmaBase+2 ; Dma Channel-1 address (CP port)
DmaCh1Count equ DmaBase+3 ; Dma Channel-1 count
DmaCh2Addr equ DmaBase+4 ; Dma Channel-2 address (Dma Test)
DmaCh2Count equ DmaBase+5 ; Dma Channel-2 count
DmaCh3Addr equ DmaBase+6 ; Dma Channel-3 address (Unused)
DmaCh3Count equ DmaBase+7 ; Dma Channel-3 count
DmaMode equ DmaBase+8 ; Commands
DmaStatus equ DmaBase+8 ; Status
DmaCh0Mask equ 1 ; Mask for Ch-0 TC Status in Dma
DmaCh1Mask equ 2 ; Mask for Ch-1 TC Status in Dma
DmaCh2Mask equ 4 ; Mask for Ch-2 TC Status in Dma
DmaCh3Mask equ 8 ; Mask for Ch-3 TC Status in Dma
DmaFuncRead equ 80H ; Dma memory read
DmaFuncWrite equ 40H ; Dma memory write
CPChannelMask equ 2 ; CP is channel 1
; Floppy Disk Controller
FDCBase equ 84H ; Bank 0a
FDCCommand equ FDCBase+0 ; Commands (write)
FDCStatus equ FDCBase+0 ; Status (Read)
FDCTrack equ FDCBase+1 ; Track Register
FDCSector equ FDCBase+2 ; Sector Register
FDCData equ FDCBase+3 ; Data Register
FDCState equ 0E8H ; External State register
FDCStatusReg equ 0E8H ; External Status register
; Printer control
PrinterBase equ 88H ; Bank 0a
PrinterData equ PrinterBase+0 ; Data (Read, write)
PrinterCommand equ PrinterBase+1 ; Commands (write)
PrinterStatus equ PrinterBase+1 ; Status (Read)
; Note: PrinterBase+2, 3 same as PrinterBase+0, 1
; Timer control
TimerBase equ 8CH ; Bank 0a
TimerCount0 equ TimerBase+0 ; Counter 0 (Read, write)
TimerCount1 equ TimerBase+1 ; Counter 1 (Read, write)
TimerCount2 equ TimerBase+2 ; Counter 2 (Read, write)
TimerMode equ TimerBase+3 ; Commands
; LSEP definitions.
LPrinterCommand equ 91H ; LSEP Uart Command
LPrinterStatus equ 91H ; LSEP Uart Status
LPrinterData equ 90H ; LSEP Uart Data
LTimerMode equ 97H ; LSEP Timer Mode
LTimerCount0 equ 94H ; LSEP Timer Counter 0
; Host address Prom.
; Start of Prom:
HostAddr equ 0B0H ; Prom has 16 addresses.
; CP interface and control.
; CP port addresses.
CPControl equ 0ECH ; CP control register:
; IOPWait',,SwTAddr',,IOPAttn,,CPDmaMode,,CPDmaIn
CPStatus equ 0ECH ; CP port status
CPIn equ 0EBH ; CP data in
CPOut equ 0EBH ; CP data out
CPDmaClr equ 0EEH ; Clear CP Dma Complete (write)
; TPC for control store read/write.
CSTask equ 6H ; TPC for control store read/write addressing
; Values for CP control register.
; Bits 0:5 - (IOPWait', SwTAddr', IOPAttn, CPDmaMode, CPDmaIn).
CPWait equ 40H ; IOPWait = 1, SwTAddr = 0
CPWaitSwT equ 00H ; IOPWait=1, SwTAddr = 1
CPEnable equ 0C0H ; IOPWait=0, SwTAddr = 0
IOPAttn equ 20H ; IOPAttn = 1
CPDmaMode equ 10H ; CPDmaMode = 1
CPDmaIn equ 8H ; CPDmaIn = 1
; CP status masks.
CPAttnMask equ 80H ; Mask of CPAttn' bit in CPStatus
CPInIntMask equ 4 ; Mask of CPIn interrupt bit in CPStatus
CPOutIntMask equ 2 ; Mask of CPOut interrupt bit in CPStatus
CPDmaCompMask equ 1 ; Mask of CP Dma complete bit in CPStatus
CPDmaMask equ 34H ; Mask of IOPAttn,DmaMode,DmaIn
; Control store.
CSBase equ 0F8H ; Bank 7
; Current description.
; Write (all CSi are complemented values):
CSa equ CSBase+0 ; CS Byte a: rA[0:3],,rB[0:3]
CSb equ CSBase+1 ; CS Byte b: aS[0:2],,aF[0:2],,aD[0:1]
CSc equ CSBase+2 ; CS Byte c: EP,,CIN,,EnSU,,mem,,fS[0:3]
CSd equ CSBase+3 ; CS Byte d: fY[0:3], INIA[0:3]
CSe equ CSBase+4 ; CS Byte e: fX[0:3], INIA[4:7]
CSf equ CSBase+5 ; CS Byte f: fZ[0:3], INIA[8:11]
TPCHigh equ CSBase+6 ; TPCaddr[0:2], TPCdata[0:4]'
TPCLow equ CSBase+7 ; (unused),,TPCdata[5:11]'
; Read:
CS0 equ CSBase+0 ; CS Byte a: rA[0:3],,rB[0:3]
CS1 equ CSBase+1 ; CS Byte b: aS[0:2],,aF[0:2],,aD[0:1]
CS2 equ CSBase+2 ; CS Byte c: EP,,CIN,,EnSU,,mem,,fS[0:3]
CS3 equ CSBase+3 ; CS Byte d: fY[0:3], INIA[0:3]
CS4 equ CSBase+4 ; CS Byte e: fX[0:3], INIA[4:7]
CS5 equ CSBase+5 ; CS Byte f: fZ[0:3], INIA[8:11]
CS6 equ CSBase+6 ; TC[0:3], TPCdata[0:3]'
CS7 equ CSBase+7 ; TPCdata[4:11]'
;Note: CSa=CS0, CSb=CS1, ... , TPCHigh=CS6, TPCLow=CS7
; Keyboard, mouse.
KBData equ 0EAH ; Keyboard data latch (read)
MouseX equ 0EDH ; Mouse X counter (read)
MouseY equ 0EEH ; Mouse Y counter (read)
MouseClr equ 0EDH ; Clear mouse X, Y counters (write)
Keyset EQU 80H
; Miscellaneous I/O addresses.
MiscInput1 equ 0EFH ; Miscellaneous input
MiscClocks1 equ 0E9H ; KB, MP, TOD clocks (write)
MiscControl1 equ 0EFH ; KB, MP, TOD control (write)
TODClr equ 0EAH ; Clear TOD interrupt (write)
; Constants for miscellaneous I/O.
; MiscConstrol1.
pReadKBData equ 40H ; Read KB data (Rev G and higher)
npReadKBData equ 0FFH-pReadKBData ; Complement of ReadKBData bit mask
KBTone equ 20H ; KB speaker bit
nKBTone equ 0FFH-KBTone ; Complement of KBTone bit mask
KBDiag equ 10H ; Set KB Diag mode
nKBDiag equ 0FFH-KBDiag ; Complement of KBDiag bit mask
BlankMPanel equ 8H ; Blank MPanel bit
nBlankMPanel equ 0FFH-BlankMPanel ; Complement of BlankMPanel bit mask
ReadTimeMode equ 4H ; Read TOD mode bit
nReadTimeMode equ 0FFH-ReadTimeMode ; Complement of ReadTimeMode bit mask
ClearTimeMode equ 2H ; Clear TOD mode bit
nClearTimeMode equ 0FFH-ClearTimeMode ; Complement of ClearTimeMode bit mask
SetTimeMode equ 1H ; Set TOD mode bit
nSetTimeMode equ 0FFH-SetTimeMode ; Complement of SetTimeMode bit mask
; MiscClocks1.
ClrMPanel equ 40H ; Clear MPanel clock
IncMPanel equ 20H ; Increment MPanel clock
TODRead equ 10H ; TOD Read clock
TODSetA equ 8H ; TOD Set clock (A)
TODSetB equ 4H ; TOD Set clock (B)
TODSetC equ 2H ; TOD Set clock (C)
TODSetD equ 1H ; TOD Set clock (D)
; MiscInput1: AltBoot,TimeData,PowerFailed,TODInt,CSParError,MouseSw1,Sw2,Sw3 (read)
AltBootMask equ 80H ; Bit 0: AltBoot bit
TODDataMask equ 40H ; Bit 1: TODData bit
PowerFailedMask equ 20H ; Bit 2: Power Failed bit
TODIntMask equ 10H ; Bit 3: Time-of-day interrupt bit
CSParityMask equ 8H ; Bit 4: CS Parity error bit (active low)
MouseSwMask equ 7H ; Bits 5-7: Mouse switches
nMouseSwMask equ 0F8H ; Complement of Mouse switch mask
; System I/O Registers
IntReq equ 0E9H ; Interrupt Request bits (read)
; Bit 0: Floppy Controller Request (low)
; Bit 1: Keyboard Request (low)
; Bit 2: Printer Tx Ready (low)
; Bit 3: Printer Rx Ready (low)
; Bit 4: Time-of-Day Request (low)
; Bit 5: RS232 Request (low)
; Bit 6: LSEP Rx Ready (low)
; Bit 7: LSEP Tx Ready (low)
IntReqMask equ 0FFH ; Mask to complement active low signals
KBReqMask equ 40H ; Keyboard Request bit
PtrTxReqMask equ 20H ; Printer transmit Request bit
PtrRxReqMask equ 10H ; Printer receive Request bit
MiscTimerReqMask EQU 8h ; misc timer request
SIOReqMask equ 4H ; RS232C Request bit
LSEPRxReqMask equ 2 ; LSEP Uart Rx request
LSEPTxReqMask equ 1 ; LSEP Uart Tx request
; RS232C/RS366
; [Z80-SIO]
SIOBase equ 98H ; SelBank1c' (IOPSel.2)
RxData equ SIOBase ; SIO Channel A Data Register
TxData equ SIOBase+1 ; SIO Channel B Data Register
RxCont equ SIOBase+2 ; SIO Channel A Control Register
TxCont equ SIOBase+3 ; SIO Channel B Control Register
; [i8253 Programmable Interval Timer (Read/Write)]
; - - - Address - - -
OSCBase equ LTimerCount0 ; Baud Rate Gen. SelBank1b' (IOPSel.1)
OSCCont equ OSCBase+3 ; Baud Rate Gen. Control Register
OSCReg equ OSCBase+1 ; Counter for SIO
TimeReg equ OSCBase+2 ; Counter for Time Counter
; [ RS366 Register (Read & Write)]
; - - - Address - - -
RS366Reg equ 9CH ; RS366 register (IOPSel.3)
; - - - Command Bit - - -
SIOLpEn equ 80H ; SIO Test Loop Back Enable Bit (Bit 0)
LocalTim equ 40H ; Local OSC Enable Bit (Bit 1)
nLocalTim EQU 0BFh ; complement of LocalTim
CallReq equ 20H ; Call Request Bit (Bit 2)
DigPr equ 10H ; Digit Present Bit (Bit 3)
; - - - Status Bit - - -
TimeUp equ 80H ; Timer
DSRdy equ 40H ; Data Set Ready
Ring equ 20H ; Ring Detected
DLO equ 10H ; Data Line Occupied
PND equ 8H ; Present Next Digit
COS equ 4H ; Call Origination Status
ACR equ 2H ; Abondon Call and Retry
PWI equ 1H ; Power Indication
; Memory configuration parameters
; Prom
EndOfProm2K equ 7FFH ; 3777B
EndOfProm8K equ 1FFFH ; 17777B
EndOfProm equ EndOfProm8K ; Set up for 8K Prom
;RAM
StartOfRAM equ 2000H ; 20000B
EndOfRAM1K equ 23FFH ; End of 1K RAM (21777B)
EndOfRAM8K equ 3FFFH ; End of 8K RAM (37777B)
EndOfRAM16K equ 5FFFH ; End of 16K RAM (57777B)
EndOfRAM equ EndOfRAM16K ; Set up for 16K RAM
; User stack pointer start location (see IOPKernelDefs).
UserStkStart equ 5FCEH
; All programs should issue this value to FDCState at the start.
DisableFDC equ 80H ; Disable floppy, set wait cycles in FDCState
; Debugging:
Skip equ 4 ; No of bytes to skip over a Breakpoint instruction
opDI EQU 0F3H ; DI op code
opJMP EQU 0C3H ; JMP op code
opJZ EQU 0CAH ; JZ op code
opJNZ EQU 0C2H ; JNZ op code
opLXIH EQU 21H ; LXI H op code
opANI EQU 0E6H ; ANI op code
opMVIA EQU 3EH ;00111110B MVI A op code
opMVIM EQU 36H ;00110110B MVI M op code
opLXID EQU 11H ; LXI D op code
opLXIB EQU 1 ; LXI B op code
opSUI EQU 0D6H ;11010110B SUI op code
opSBI EQU 0DEH ;11011110B SBI op code
opCPI EQU 0FEH ;11111110B CPI op code
opSHLD EQU 22H ;00100010B SHLD op code
opLHLD EQU 2AH ;00101010B LHLD op code
opCALL EQU 0CDH ;11001101B CALL op code
opORI EQU 0F6H ;11110110B ORI op code
END SysDefs