DIRECTORY
Basics USING [DoubleShiftLeft],
DebuggerDefs,
DragOpsCross USING [],
--Word, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, bytesPerPage, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, RegIndex, PadByte, Lit8, Op4, Op8, JDist8, Inst, OIFormat, OQBformat, LRformat, QRformat, ShortRegQR, OBformat, LRBformat, RRformat, ODBformat, LRRBformat, RJBformat, ShortRegRJB, JBBformat, TrapWidthWords, TrapWidthBytes, XopBase, TrapBase, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondFalse, ALUCondEZ, ALUCondLZ, ALUCondLE, ALUCondSpare, ALUCondNE, ALUCondGE, ALUCondGZ, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, ALUCondNotOver, ALUCondNB, ALUCondNI, ModeFault, MemAccessFault, IOAccessFault, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euToKBus, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuSLimit, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, EURegs, EULegalRegs, IFURegs, IFULegalRegs, StackedStatusWord, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest, IOOperand, PCmdFormat, PCmdByteSelect, PCmdClass, PCmdSpace, PCmdDirection
DragOpsCrossUtils USING [CardToWord],
--InstToBytes, InstToFormat, BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, XopToBytePC, TrapIndexToBytePC, FieldUnit
HandCoding,  --Has opcode and register defs.
HandCodingPseudos,  --Label, SetLabel, GenLabel, GenLabelHere, UseLabel8A, UseLabel8B, UseLabel16, UseLabel32, LReg, PReg, SReg, AddReg, SubReg, SetRegConst, MoveReg, MoveRegI, LRegI, IndexedJump, ProcedureEntry, ProcedureExit, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetYoungestPC, GetYoungestStatus, GetEldestPC, GetEldestStatus, SetYoungestPC, SetYoungestStatus, SetEldestPC, SetEldestStatus, Pause, Halt
HandCodingSupport;  --Area, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetCurrentArea, LoadArea, GetOutputPC, SetOutputPC, WordAlign, ReserveData, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord

GenRW: CEDAR PROGRAM
IMPORTS Basics, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport
= BEGIN OPEN DebuggerDefs, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport;

aux0: AuxRegSpec = [aux[0]];
aux1: AuxRegSpec = [aux[1]];
aux2: AuxRegSpec = [aux[2]];
aux3: AuxRegSpec = [aux[3]];
aux4: AuxRegSpec = [aux[4]];
aux5: AuxRegSpec = [aux[5]];
aux6: AuxRegSpec = [aux[6]];
aux14: AuxRegSpec = [aux[14]];
aux15: AuxRegSpec = [aux[15]];
const5: ConstSpec = [const[5]];
const6: ConstSpec = [const[6]];
const7: ConstSpec = [const[7]];
const8: ConstSpec = [const[8]];
const9: ConstSpec = [const[9]];
const10: ConstSpec = [const[10]];
const11: ConstSpec = [const[11]];


All: PROC = {

area: Area = GetCurrentArea[];

ReserveSpace: PROC [addr, nwords: CARD] = {
oldPC: LONG CARDINAL = GetOutputPC[area];
bytePC: LONG CARDINAL _ Basics.DoubleShiftLeft[[lc[addr]], 2].lc;
SetOutputPC[bytePC];	--pc is a byte address
FOR I: CARD IN [0..nwords) DO
OutputWord[area, CardToWord[0], FALSE];
ENDLOOP;
SetOutputPC[oldPC];
};

GenData: PROC [] ~ {
wval: LONG CARDINAL _ 1;
baseAddr: LONG CARDINAL _ 1400000B;
ReserveSpace[baseAddr, 32];
drLIQB[CardToWord[baseAddr]];  --reg0 _ base register for writes and reads
FOR I: CARDINAL IN [0..32) DO
drLIQB[CardToWord[wval]];
wval _ Basics.DoubleShiftLeft[[lc[wval]], 1].lc;
drSRIn[reg0, I];
ENDLOOP;
wval _ 1;
FOR I: CARDINAL IN [0..32) DO
rdOK: Label = GenLabel[];
drLRIn[reg0, I];
drLIQB[CardToWord[wval]];
wval _ Basics.DoubleShiftLeft[[lc[wval]], 1].lc;
drRJEBJ[popSrc, belowSrcPop, UseLabel8B[rdOK]]; Pause[]; SetLabel[rdOK];
ENDLOOP;
drASL[377B];  --Clear the stack
};

GenAddr: PROC [] ~ {
wval: LONG CARDINAL _ 1;
baseAddr: LONG CARDINAL = 1400000B;
upperDisp: CARDINAL = IF withSoftCard THEN 17 ELSE 30;
FOR I: CARDINAL IN [0..upperDisp) DO
ReserveSpace[baseAddr + wval, 1];
drLIQB[CardToWord[wval + baseAddr]];  --reg0 _ memory reference address
wval _ Basics.DoubleShiftLeft[[lc[wval]], 1].lc;
drLIB[I];
drSRIn[reg0, 0];
drDIS[];
ENDLOOP;
wval _ 1;
drLIQB[CardToWord[baseAddr]]; --reg0 _ base address
FOR I: CARDINAL IN [0..upperDisp) DO
rdOK: Label = GenLabel[];
drLIQB[CardToWord[wval]];
wval _ Basics.DoubleShiftLeft[[lc[wval]], 1].lc;
drRRX[topDst, reg0, topSrc];
drJEBBJ[I, UseLabel8B[rdOK]]; Pause[]; SetLabel[rdOK];
ENDLOOP;
drASL[377B];  --Clear the stack
};

GenRWAll: PROC [] ~ {
RWTest: PROC [baseAddr, dval: LONG CARDINAL] ~ {
LRI0ok: Label = GenLabel[];
LRI13ok: Label = GenLabel[];
RRIok: Label = GenLabel[];
ReadBackBad: Label = GenLabel[];
ReadBackBad1: Label = GenLabel[];
ReadBackBad2: Label = GenLabel[];
dvalx: LONG CARDINAL _ dval;
ReserveSpace[baseAddr, 42];
FOR I: CARDINAL IN [0..16) DO
drLIQB[CardToWord[baseAddr + LONG[I]]];
ENDLOOP;
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg0, 0];  --baseAddr
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg1, 1];  --baseAddr + 2
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg2, 2];  --baseAddr + 4
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg3, 3];  --baseAddr + 6
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg4, 4];  --baseAddr + 8
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg5, 5];  --baseAddr + 10
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg6, 6];  --baseAddr + 12
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg7, 7];  --baseAddr + 14
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg8, 8];  --baseAddr + 16
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg9, 9];  --baseAddr + 18
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg10, 10];  --baseAddr + 20
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg11, 11];  --baseAddr + 22
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg12, 12];  --baseAddr + 24
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg13, 13];  --baseAddr + 26
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg14, 14];  --baseAddr + 28
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1; drSRIn[reg15, 15];  --baseAddr + 30

drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drLIQB[CardToWord[baseAddr + 16]];
drWB[16];	--baseAddr + 32

drLIQB[CardToWord[baseAddr + 17]];
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drWSB[17];	--baseAddr + 34

drLIQB[CardToWord[baseAddr + 18]];
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drPSB[18];	--baseAddr + 36
drDIS[];

dvalx _ dval;
drLRIn[reg0, 0]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJEBJ[popSrc, belowSrcPop, UseLabel8B[LRI0ok]]; SetLabel[ReadBackBad]; Pause[]; SetLabel[LRI0ok];
drLRIn[reg1, 1]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg2, 2]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg3, 3]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg4, 4]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg5, 5]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg6, 6]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg7, 7]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg8, 8]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg9, 9]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg10, 10]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg11, 11]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg12, 12]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad]];
drLRIn[reg13, 13]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJEBJ[popSrc, belowSrcPop, UseLabel8B[LRI13ok]]; SetLabel[ReadBackBad1]; Pause[]; SetLabel[LRI13ok];
drLRIn[reg14, 14]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];
drLRIn[reg15, 15]; drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];

drLIQB[CardToWord[baseAddr + 16]];
drRB[16];	--baseAddr + 32
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];

drLIQB[CardToWord[baseAddr + 17]]; drLIB[17];
drQRX[pushAtop, belowSrc];
drLIQB[CardToWord[dvalx]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];
drRRX[belowDst, popSrc, belowSrc];
drLIQB[CardToWord[dvalx]]; dvalx _ dvalx + 1;

drLIQB[CardToWord[baseAddr + 18]];
drRSB[18];	--baseAddr + 36
drLIQB[CardToWord[dvalx]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];
drLIB[18];
drRX[];	--baseAddr + 36 again
drLIQB[CardToWord[dvalx]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];
drLIQB[CardToWord[baseAddr + 18]];
drROR[aux0, popSrc, topSrc];
drLGF[18];	--baseAddr + 36 again
drLIQB[CardToWord[dvalx]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[ReadBackBad1]];

drLIQB[CardToWord[baseAddr]];
drSRn[reg0];
drWRI[reg1, reg0, 38];

drLIQB[CardToWord[baseAddr + 20]];
drROR[aux2, popSrc, topSrc];
drWAI[reg3, aux2, 20];

drRRI[reg15, reg0, 38];
drLRn[reg15];
drRJEBJ[popSrc, reg1, UseLabel8B[RRIok]]; SetLabel[ReadBackBad2]; Pause[]; SetLabel[RRIok];

drRAI[reg4, aux2, 20];
drLRn[reg4];
drRJNEB[popSrc, reg3, UseLabel8B[ReadBackBad2]];
drASL[377B];  --Clear stack
};

RWTest[1220100B, 12345670123B];
RWTest[1220200B, 11111111111B];
RWTest[1220300B, 22222222222B];
RWTest[1220400B, 33333333333B];
IF massiveTesting THEN {
RWTest[1220500B, 04444444444B];
RWTest[1220600B, 25252525252B];
RWTest[1220700B, 12525252525B];
};
};

GenCST: PROC [] ~ {
CSTTest: PROC [addr, instore, old, new: CARD, alpha: CARDINAL] ~ {
STbad: Label = GenLabel[];
STok0: Label = GenLabel[];
drASL[255];
drLIQB[CardToWord[addr - alpha]];  --base register
drLIQB[CardToWord[instore]];
drSRIn[reg0, alpha];  --Mem(addr) _ instore
drLIQB[CardToWord[new]];  --[S-1] = new value conditionally stored
drLIQB[CardToWord[old]];  --[S] = old value compared against storage
drCST[alpha];
drLIQB[CardToWord[instore]];
drRJEBJ[popSrc, belowSrcPop, UseLabel8B[STok0]]; SetLabel[STbad]; Pause[]; SetLabel[STok0];
drLIQB[CardToWord[old]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[STbad]];  --Fails if stack screwed up
drLRIn[reg0, alpha];
IF instore = old THEN {  --Store should succeed
drLIQB[CardToWord[new]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[STbad]];  --Fails if new not stored
}
ELSE {  --Store should fail
drLIQB[CardToWord[instore]];
drRJNEB[popSrc, belowSrcPop, UseLabel8B[STbad]];  --Fails if new stored
};
};

ReserveSpace[1221000B, 1];
CSTTest[1221000B, 11111111111B, 11111111111B, 12341234123B, 300B];  --Succeed
CSTTest[1221000B, 11111111111B, 22222222222B, 12312312312B, 377B];  --Fail
};


GenData[];
GenAddr[];
GenRWAll[];
IF NOT withSoftCard THEN GenCST[];

Halt[177777B];	--Terminate here at the end of the program
};


END.

zGenRW.mesa
Copyright c 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.
Edward Fiala February 7, 1986 1:03:42 pm PST
Curry, September 11, 1986 11:41:17 pm PDT
Curry, September 11, 1986 11:40:46 pm PDT const2 => const7
Fiala November 5, 1986 6:04:33 pm PST Cosmetic edits.
Fiala March 27, 1987 2:57:10 pm PST Eliminate Reset, Halt, and Pause stuff
to run with GenDebugger; eliminate FillXop, FillTrap, and entry labels; do not do GenCST when withSoftCard = TRUE; add massiveTesting conditional.

Load with "quad -cx GenDebugger GenRW".  This diagnostic tests P bus data and addressing and all opcodes which read or write memory.  When correctly executed with DebuggerDefs.massiveTesting = TRUE and withSoftCard = TRUE, it terminates with a HALT[177777b] at PC = 4050713B on instruction 1292 cycle 4101.  When correctly executed with DebuggerDefs.massiveTesting = FALSE, it terminates with a HALT[177777b] at PC = ? on instruction ? cycle ?.

**Since Lizard requires byte addresses, the top two memory address bits cannot be tested.

In this diagnostic, the auxiliary registers are called aux0, aux1, ..., aux15; the locals are called reg0, reg1, ..., reg15; and the constants are called const0, const1, ..., const15.
  const7 contains -1.
The Lizard simulator requires that all storage touched by a program be declared in advance; for data areas touched by EU memory references, this procedure is used to declare words that will be touched.  **Maybe Lizard requires only that each page touched by a program be reserved by a single OutputWord??
Test P bus data by writing data values with each bit in 0 and 1 states.
**Need code to setup the map for the references here somewhere.
Test P bus addressing by writing at addresses with each address bit in 0 and 1 states.
139 instructions tests all the memory writes and reads by first writing at addresses just above baseAddr using all the different memory write opcodes and then reading back the values using all the memory read opcodes and testing the data.
Here we want reg0 + 38 = baseAddr + 38 to be the address and reg1 to hold the data being written.
Here we want aux2 + 20 = baseAddr + 40 to be the address and reg3 to hold the data being written.
Here we want reg0 + 38 to be the address and reg15 to receive the data being read.
Here aux2 + 20 = baseAddr + 40 is the address and reg4 receives the data being read.
[S+1] _ Mem([S-2] + AlphaZ); if [S+1] = [S] then Mem([S-2] + AlphaZ) _ [S-1]; S _ S+1.
Begin at PC = userBasePC = 1010000B * 4, L = 1, S = 0 as established in GenDebugger.  const0 is in a ROM, so it requires no initialization; the other constants require no initialization for this diagnostic.

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