[Cyan]<DragonWare0.1>Diagnostics>GenFieldUnit.mesa!1

GenFieldUnit.mesa

Edward Fiala February 7, 1986 11:46:08 am PST

Curry, September 11, 1986 11:07:50 pm PDT

Curry, September 11, 1986 12:27:21 pm PDT drSHD => drSHDL, const2 => const7 = -1, const3 => const8 = enabling flag

Fiala November 5, 1986 5:53:38 pm PST Cosmetic edits; added tests for SHDR.

Fiala March 26, 1987 2:45:23 pm PST Eliminate Reset, Halt, and Pause stuff
to run with GenDebugger; eliminate FillXop, FillTrap, and entry labels.

Fiala April 10, 1987 12:49:18 pm PST Remove tests for which mask < shift & insert = TRUE (illegal).

Load with "quad -cx GenDebugger GenFieldUnit". This diagnostic tests the Field Unit opcodes SHL, SHR, SHDL, SHDR, RFU, and FSDB. When correctly executed with massiveTesting = FALSE, it terminates with a HALT[177777b] at PC = 4200465B on instruction 13427 cycle 31004. When correctly executed with massiveTesting = TRUE, it terminates with a HALT[177777b] at PC = 4200465B on instruction 13427 cycle 31004.

DIRECTORY

Basics USING [DoubleShiftLeft, DoubleShiftRight, DoubleAnd, DoubleOr, DoubleNot, LongNumber],

DebuggerDefs,

DragOpsCross USING [],
--Word, wordsPerPage, bytesPerWord, charsPerWord, bitsPerByte, bitsPerCharacter, bitsPerWord, bytesPerPage, logWordsPerPage, logBitsPerByte, logBitsPerChar, logBytesPerWord, logCharsPerWord, logBitsPerWord, logBytesPerPage, PageCount, PageNumber, maxPagesInVM, SixBitIndex, FiveBitIndex, TwoWords, FourBitIndex, Half, ThreeBitIndex, FourHalves, TwoHalves, Byte, ZerosByte, OnesByte, EightBytes, FourBytes, ByteIndex, BytesPerWord, TwoBytes, Comparison, ByteAddress, WordAddress, FieldDescriptor, RegIndex, PadByte, Lit8, Op4, Op8, JDist8, Inst, OIFormat, OQBformat, LRformat, QRformat, ShortRegQR, OBformat, LRBformat, RRformat, ODBformat, LRRBformat, RJBformat, ShortRegRJB, JBBformat, TrapWidthWords, TrapWidthBytes, XopBase, TrapBase, KernalLimit, TrapIndex, StackUnderflowTrap, IFUPageFaultTrap, ResetTrap, IFUStackOverflowTrap, EUStackOverflowTrap, RescheduleTrap, ALUCondFalse, ALUCondEZ, ALUCondLZ, ALUCondLE, ALUCondSpare, ALUCondNE, ALUCondGE, ALUCondGZ, ALUCondOver, ALUCondBC, ALUCondIL, ALUCondDO, ALUCondNotOver, ALUCondNB, ALUCondNI, ModeFault, MemAccessFault, IOAccessFault, EUPageFault, EUWriteFault, AUFault, euStack, euJunk, euToKBus, euMAR, euField, euConstant, euAux, euBogus, euLast, ifuYoungestL, ifuYoungestPC, ifuEldestL, ifuEldestPC, ifuSLimit, ifuBogus, ifuL, ifuS, ifuPC, ifuLast, EURegs, EULegalRegs, IFURegs, IFULegalRegs, StackedStatusWord, IFUStackIndex, IFUStackSize, IFUOverflow, EUStackIndex, EUStackSize, EULocalIndex, EULocals, EUAuxIndex, EUAuxRegs, EUConstIndex, EUConstants, IOLocation, ioRescheduleRequest, ioResetRequest, IOOperand, PCmdFormat, PCmdByteSelect, PCmdClass, PCmdSpace, PCmdDirection

DragOpsCrossUtils USING [CardToWord],
--InstToBytes, InstToFormat, BytePCToWordAddress, WordAddressToBytePC, IOOperandToCard, CardToIOOperand, FieldDescriptorToCard, CardToFieldDescriptor, BytesToWord, BytesToHalf, WordToBytes, HalfToBytes, HalvesToWord, WordToHalves, HighHalf, LowHalf, LeftHalf, RightHalf, SwapHalves, WordToInt, IntToWord, WordToCard, HalfToCard, ByteToCard, CardToWord, CardToHalf, CardToByte, DragAnd, DragOr, DragXor, DragNot, VanillaAdd, VanillaSub, AddDelta, HalfNot, HalfAnd, HalfOr, HalfXor, HalfShift, DoubleWordShiftLeft, SingleWordShiftLeft, SingleWordShiftRight, XopToBytePC, TrapIndexToBytePC, FieldUnit

HandCoding, --Has opcode and register defs.

HandCodingPseudos, --Label, SetLabel, GenLabel, GenLabelHere, UseLabel8A, UseLabel8B, UseLabel16, UseLabel32, LReg, PReg, SReg, AddReg, SubReg, SetRegConst, MoveReg, MoveRegI, LRegI, IndexedJump, ProcedureEntry, ProcedureExit, SetupField, ExtractField, ShiftLeft, LoadProcessorReg, StoreProcessorReg, CauseReschedule, CauseReset, GetSPLimit, SetSPLimit, GetYoungestPC, GetYoungestStatus, GetEldestPC, GetEldestStatus, SetYoungestPC, SetYoungestStatus, SetEldestPC, SetEldestStatus, Pause, Halt

HandCodingSupport; --Area, GetProc, PutProc, ProcList, NewArea, GenWithArea, Gen1WithArea, ForceOut, GetCurrentArea, LoadArea, GetOutputPC, SetOutputPC, WordAlign, ReserveData, OutputByte, OutputOneByte, OutputAlphaBeta, OutputAlphaBetaGammaDelta, OutputWord

GenFieldUnit: CEDAR PROGRAM

IMPORTS Basics, DragOpsCrossUtils, HandCoding, HandCodingPseudos

= BEGIN OPEN DebuggerDefs, DragOpsCrossUtils, HandCoding, HandCodingPseudos, HandCodingSupport;

In this diagnostic, the auxiliary registers are called aux0, aux1, ..., aux15; the locals are called reg0, reg1, ..., reg15; and the constants are called const0, const1, ..., const15.

aux0: AuxRegSpec = [aux[0]];

aux1: AuxRegSpec = [aux[1]];

aux2: AuxRegSpec = [aux[2]];

aux3: AuxRegSpec = [aux[3]];

aux4: AuxRegSpec = [aux[4]];

aux5: AuxRegSpec = [aux[5]];

aux6: AuxRegSpec = [aux[6]];

aux14: AuxRegSpec = [aux[14]];

aux15: AuxRegSpec = [aux[15]];

const5: ConstSpec = [const[5]];

const6: ConstSpec = [const[6]];

const7: ConstSpec = [const[7]];

const8: ConstSpec = [const[8]];

const9: ConstSpec = [const[9]];

const10: ConstSpec = [const[10]];

const11: ConstSpec = [const[11]];

BugTrap: SIGNAL = CODE;

All: PROC = {

--area: Area = GetCurrentArea[];

A field descriptor is a special interpretation of a 16-bit quantity used to control the Field Unit.

FieldDescriptor: TYPE = MACHINE DEPENDENT RECORD [

reserved: [0..7] ← 0,

reserved bits, not currently used, but must be 0s

insert: BOOL ← FALSE,

governs choice of background and low bits of mask

mask: [0..32] ← 32,

32-mask gives start pos of 1s in the mask (mask = 0 => no 1s)

shift: [0..32] ← 0

gives # of bits to left-shift the double word

];

Test FSDB (FieldDescriptor ← [S] + AlphaBeta; S ← S - 1); this doesn't really test the loading of the shift control hardware because LIP reads the value from a shadow register.

GenFSDB: PROC [] ~ {

FSDBTest: PROC [s: LONG CARDINAL, ab: CARDINAL] ~ {

sw: Word ← CardToWord[s];

resw: Word ← CardToWord[s + ab];

drLIQB[sw]; drFSDB[ab]; drLIQB[resw];

drLIP[131]; --read the field register

drRJEBJ[popSrc, belowSrcPop, 4B]; Pause[];

};

FSDBTest[0, 0];

FSDBTest[0, 1];

FSDBTest[0, 2];

FSDBTest[0, 4];

FSDBTest[0, 10B];

FSDBTest[0, 20B];

FSDBTest[0, 40B];

FSDBTest[0, 100B];

FSDBTest[0, 200B];

FSDBTest[0, 400B];

FSDBTest[0, 1000B];

FSDBTest[0, 2000B];

FSDBTest[0, 4000B];

FSDBTest[17777B, 0];

FSDBTest[17777B, 1];

FSDBTest[17777B, 2];

FSDBTest[17777B, 4];

FSDBTest[17777B, 10B];

FSDBTest[17777B, 20B];

FSDBTest[17777B, 40B];

FSDBTest[17777B, 100B];

FSDBTest[17777B, 200B];

FSDBTest[17777B, 400B];

FSDBTest[17777B, 1000B];

FSDBTest[17777B, 2000B];

FSDBTest[17777B, 4000B];

FSDBTest[13456B, 0];

FSDBTest[11111B, 1];

FSDBTest[12222B, 2];

FSDBTest[13333B, 4];

FSDBTest[14444B, 10B];

FSDBTest[16666B, 20B];

FSDBTest[15555B, 40B];

FSDBTest[10000B, 100B];

FSDBTest[01234B, 200B];

FSDBTest[02345B, 400B];

FSDBTest[03456B, 1000B];

FSDBTest[04567B, 2000B];

FSDBTest[05670B, 4000B];

};

For a pair of inputs and shifter control values, determine the FieldDescriptor and output result for the shifter. Shifter input is the left word in [0..32) and right word in [32..64); this quantity is left-shifted by the specified count, and the left-most 32 bits of the result are the output (so a shift of 0 delivers the left input word, while a shift of 32 delivers the right input word at the output). The mask is used as a multiplexor to select bits from either the shifter output or the background word.

FUSim: PROC [left, right: LONG CARDINAL, insert: BOOLEAN, mask, shift: CARDINAL] RETURNS[out: Word, ab: CARDINAL] ~ {

output: LONG CARDINAL;

shifted: LONG CARDINAL ← Basics.DoubleShiftLeft[[lc[left]], shift].lc + Basics.DoubleShiftRight[[lc[right]], 32 - shift].lc;

mMask: LONG CARDINAL ← Basics.DoubleShiftRight[[lc[37777777777B]], 32 - mask].lc;

IF insert THEN {

IF mask < shift THEN BugTrap[]; --would be no insert; illegal for hardware

mMask ← Basics.DoubleAnd[[lc[mMask]], Basics.DoubleShiftLeft[[lc[37777777777B]], shift]].lc;

output ← Basics.DoubleOr[Basics.DoubleAnd[[lc[shifted]], [lc[mMask]]], Basics.DoubleAnd[[lc[right]], Basics.DoubleNot[[lc[mMask]]]]].lc;

}

ELSE output ← Basics.DoubleAnd[[lc[shifted]], [lc[mMask]]].lc;

RETURN[CardToWord[output], (IF insert THEN 10000B ELSE 0) + (mask * 64) + shift];

};

Test SHL, SHR, SHDL, and SHDR on each value of the shift count.
SHL = [S] ← FieldUnit[[S], 0, AlphaBeta].
SHR = [S] ← FieldUnit[[S], [S], AlphaBeta].
SHDL = [S-1] ← FieldUnit[[S-1], [S], AlphaBeta]; S ← S - 1.
SHDR = [S-1] ← FieldUnit[[S], [S-1], AlphaBeta]; S ← S - 1.
RFU = [Rc] ← FieldUnit[[Ra], [Rb], FieldDescriptor].

GenSH: PROC [] ~ {

TestSHOp executes 21 instructions to test FSDB, SHR, SHL, SHDL, SHDR, and RFU on a particular input, shift, and mask.

TestSHOp: PROC [left, right: LONG CARDINAL, insert: BOOLEAN, mask, shift: CARDINAL] ~ {

leftw: Word ← CardToWord[left];

rightw: Word ← CardToWord[right];

result0, result1: Word;

control0, control1: CARDINAL;

SHBad: Label = GenLabel[];

[result0, control0] ← FUSim[left, right, insert, mask, shift];

drLIQB[CardToWord[LONG[control0 - mask]]];

drFSDB[mask];

drLIQB[leftw]; --into reg0

IF left # 0 THEN { --Relatively uninteresting if both inputs are 0

drDUP[]; --Duplicate the left word for the SHR and SHL tests

drDUP[];

[result1, control1] ← FUSim[left, left, insert, mask, shift];

drSHR[control1];

drLIQB[result1];

drRJNEB[popSrc, belowSrcPop, UseLabel8B[SHBad]];

[result1, control1] ← FUSim[left, 0, insert, mask, shift];

drSHL[control1];

drLIQB[result1];

drRJNEB[popSrc, belowSrcPop, UseLabel8B[SHBad]];

};

drLIQB[rightw]; --into reg1

drRFU[const5, reg0, reg1];

drSHDL[control0];

drLIQB[result0];

drRJEBJ[topSrc, const5, 4B]; SetLabel[SHBad]; Pause[];

drRJNEB[popSrc, belowSrc, UseLabel8B[SHBad]];

drLIQB[rightw];

drLIQB[leftw];

drSHDR[control0];

drRJNEB[popSrc, belowSrcPop, UseLabel8B[SHBad]];

};

TestSH: PROC [left, right: LONG CARDINAL] ~ {

FOR I: CARDINAL IN [0..32] DO

TestSHOp[left, right, FALSE, 32, I]; --All values of shift for a mask of 32

TestSHOp[left, right, FALSE, I, 0]; --All values of mask for a shift of 0

ENDLOOP;

TestSHOp[left, right, FALSE, 1, 1];

TestSHOp[left, right, FALSE, 1, 2];

TestSHOp[left, right, FALSE, 1, 4];

TestSHOp[left, right, FALSE, 1, 8];

TestSHOp[left, right, FALSE, 1, 16];

TestSHOp[left, right, FALSE, 1, 32];

TestSHOp[left, right, FALSE, 2, 1];

TestSHOp[left, right, FALSE, 2, 2];

TestSHOp[left, right, FALSE, 2, 4];

TestSHOp[left, right, FALSE, 2, 8];

TestSHOp[left, right, FALSE, 2, 16];

TestSHOp[left, right, FALSE, 2, 32];

TestSHOp[left, right, FALSE, 4, 0];

TestSHOp[left, right, FALSE, 4, 1];

TestSHOp[left, right, FALSE, 4, 2];

TestSHOp[left, right, FALSE, 4, 4];

TestSHOp[left, right, FALSE, 4, 8];

TestSHOp[left, right, FALSE, 4, 16];

TestSHOp[left, right, FALSE, 4, 32];

TestSHOp[left, right, FALSE, 8, 1];

TestSHOp[left, right, FALSE, 8, 2];

TestSHOp[left, right, FALSE, 8, 4];

TestSHOp[left, right, FALSE, 8, 8];

TestSHOp[left, right, FALSE, 8, 16];

TestSHOp[left, right, FALSE, 8, 32];

TestSHOp[left, right, FALSE, 16, 1];

TestSHOp[left, right, FALSE, 16, 2];

TestSHOp[left, right, FALSE, 16, 4];

TestSHOp[left, right, FALSE, 16, 8];

TestSHOp[left, right, FALSE, 16, 16];

TestSHOp[left, right, FALSE, 16, 32];

These are the inserts.

FOR I: CARDINAL IN [0..32] DO

TestSHOp[left, right, TRUE, 32, I]; --All values of shift for a mask of 32

TestSHOp[left, right, TRUE, I, 0]; --All values of mask for a shift of 0

ENDLOOP;

For shift >= mask, the output should always be the right input and no insert takes place; these seemed uninteresting and are done only when massiveTesting = TRUE. The hardware spec is that these are all illegal, but I try to test the ones with mask = shift anyway.

IF massiveTesting THEN {

TestSHOp[left, right, TRUE, 1, 1];

TestSHOp[left, right, TRUE, 2, 2];

TestSHOp[left, right, TRUE, 4, 4];

TestSHOp[left, right, TRUE, 8, 8];

TestSHOp[left, right, TRUE, 16, 16];

};

TestSHOp[left, right, TRUE, 2, 1];

TestSHOp[left, right, TRUE, 4, 1];

TestSHOp[left, right, TRUE, 4, 2];

TestSHOp[left, right, TRUE, 8, 1];

TestSHOp[left, right, TRUE, 8, 2];

TestSHOp[left, right, TRUE, 8, 4];

};

TestSH[37777777777B, 0];

TestSH[0, 37777777777B];

TestSH[11111111111B, 12345670123B];

TestSH[33333333333B, 23423423423B];

};

Begin at PC = userBasePC = 1010000B * 4, L = 1, S = 0 as established in GenDebugger. const0 is in a ROM, so it requires no initialization; the other constants require no initialization for this diagnostic.

GenFSDB[];

GenSH[];

Halt[177777B]; --Terminate here at the end of the program

};

END.