May, 1988; Structure Deduction Have to rename all descendants, because full names are attached directly to each wire & port, rather than distributed along paths. May, 1988; `pair' cells & array flattening All the arrays in the mips-x pc are structured as n/2 pair cells, where the pair cell contains two instances of the real element cell. So we make a procedure for deducing the array structure of an unorganized cell, and a procedure for flattening an array of arrays into an array. When deducing array structure, we need to know which subcell gets which index. And when flattening, we need to know a logical index-transformation that tells how the inner array's indices relate to the resultant array's. Can sometimes get some of this information from the connectivity; in the other times, it doesn't matter what we choose, because they're all flat-structure equivalent. June, 1988; use physcial info to guide array index deduction and flattening Rather than think real hard and deal with partial constraints, we can keep the physical info from the .ext files and use that to tell us what to do. Check that the connectivity allows it. June, 1988; interleaved port & wire structure Result of deducing pair structure and flattening outer arrays is that resultant arrays have pairs of n/2-bit busses, rather than n-bit busses. Given a situation with interleaved busses, can restructure, and propogate restructuring upward. Given n-bit array, can find interleaving, and restructure. In fact, we do this at the end of the flattening. June, 1988; Cleanup Tired of crap cluttering things up. Make cleanup operation to: (a) remove ports that don't export anything; (b) remove ports that aren't used on the outside; (c) remove wires that aren't connected to anything; and (d) remove empty and unused cell types. Doing (a) adds opportunities for both (a) and (b), but doing (b) only adds opportunities for more (b). So we have two passes: first, upward, do (a); then, downward, do (b). We do (c) during both these passes. Finally, upward, do (d). June 2X, 1988; Cleanup Can't always delete ports! Because of arrays. Element ports hold connected static components together; deleting element ports might partition a previously connected component. We decide that before any ports are deleted, we must consider whether there are bad consequences. Don't have to think hard when restructuring ports because we check that there are no arrays of the cell type. June 26, 1988; Cleanup May delete array element ports regardless of how array ports export them. Because we can always simply delete the ancestors of the array ports that directly die. Of course, we still need to test whether it's OK to delete those array ports. AASEU (Static Edges Uniform) means we have to think real hard about whether it's OK to delete element ports. AAOTSE (only top stat edges are explicitly present) means we may have to add StatEdges, as well as remove them. June 28, 1988; Cleanup Cleanup only deletes whole trees of ports, which means we don't have to think hard about AASEU. Except that checking for permission to delete ports is recursive up the call order, and might consider non-whole-trees in recursion. But making it `timid' avoids that problem. June 29, 1988; Merge Ports lacking outer distinctions Must seed with something reasonable at root. For mips-x pc, merge all gnds and merge all vdds. We are finding non-power merges --- perhaps they are all because of `cruft'? June 30, 1988; Merge Ports lacking outer distinctions Can only do it to arrays if it can be effected by adding static edges. July 5, 1988; printing Made all printout in standard order, so can use `diff'-style comparisons on printouts. July 10, 1988; Simplifying arrays Can easily drop physical information from entire design at once. Can then usually reduce every array's period to 1,1; exception (due to simple-minded impl) seen for arrays whose size and period are 1,2 --- but they're irrelevent because by this time they are unused and just waited to be garbage-collected. July 15, 1988; Split nodes Started attacking problem of two Phi2_b nodes in `addtop' by renaming them to Phi2_b/1 and Phi2_b/2. Crapped out at `Prefixify' stage (because it assumed that every name has exactly one step). Decided instead to pursue suffixes to name. July 20, 1988; Label cells pcdrvlabs and pcucntlabs add names to wires in pccntdrvs. Tried simply making the port & wire names in the label cells global, but that hurts because they get sorted earlier than power & gnd because they're global! Should we introduce the concept of label cells, or call this a crock of the mipsx methodology? July 25, 1988; Merge Ports lacking outer distinctions Every merge is because of either 1) cruft, 2) unlabelled, 3) merging generic inputs to subcells with specific signals (e.g., merging {Psi1PC, p0/clk, p1/clk} of cmfsm). Only merges we don't want are the ones that will fail (e.g., merging the ResetVector_b's and gnd's of pcdis2sl[0:0:307][0:15:220](pcdisout.pcd)). Am able to implement a `merge as much as works' procedure, which filters out the ResetVector_b's from the gnd's of pcdis2sl[0:0:307][0:15:220](pcdisout.pcd). Aug 1, 1988; Merge Ports lacking outer distinctions When refining by connections at a given site, might have a port `with no connection' because either 1) my representation for arrays omits DumbWires with only one connection, or 2) the port might be a bus, all of whose elements are connected to the same one thing (e.g., wiring a 32-bit input bus of a latch to vdd or gnd). RLichen.log Last tweaked by Mike Spreitzer on August 1, 1988 3:12:52 pm PDT ‌تطک™ Icode™?—Jکhead2کJک‚—ک*Jکں—کKJک¼—ک-Jکق—کJکî—کJکƒ—کJکٌJڑœدeœ‌œ‌œبکف—کJڑœ‘ک‘—ک5Jک—ک5JکF—کJکV—ک!Jک³—کJڑœîکî—ڑœکJڑœ·ک·—ک5Jکع—ک3Jکآ—Jک—…—¾è