
    <<LichenDataStructure.Mesa>>
        <<Last tweaked by Mike Spreitzer on May 9, 1988 1:46:29 pm PDT>>

    DIRECTORY AbSets, Basics, BasicTime, BiRels, FS, IntStuff, LichenIntBasics, Rope, SetBasics;

    LichenDataStructure: CEDAR DEFINITIONS
        IMPORTS AbSets, BiRels, IntStuff, SetBasics
        =
BEGIN
    OPEN Sets:AbSets, LichenIntBasics;
<<SIGNALs and ERRORs>>
    nyet: ERROR --not yet implemented--;

    Warning: SIGNAL [msg: ROPE, v1, v2, v3, v4, v5: REF ANY _ NIL];

    Error: ERROR [msg: ROPE, v1, v2, v3, v4, v5: REF ANY _ NIL];
<<Familiar Stuff>>
    LNAT: TYPE ~ INT--[0 .. INT.LAST]--;
    LORA: TYPE ~ LIST OF REF ANY;
    LOLORA: TYPE ~ LIST OF LORA;
    LOI: TYPE ~ LIST OF INT;
    ROPE: TYPE ~ Rope.ROPE;
    RopeList: TYPE ~ LIST OF ROPE;
    LOR: TYPE ~ LIST OF ROPE;
    LOLOR: TYPE ~ LIST OF LOR;
    Time: TYPE ~ RECORD [BasicTime.GMT]; --so we can discriminate REFS to them; you can't discriminate REFS to opaque types, and 
    BasicTime.GMT is opaque.
    Dim2: TYPE ~ LichenIntBasics.Dim2;
    Int2: TYPE ~ LichenIntBasics.Int2;
    Range2: TYPE ~ LichenIntBasics.Range2;

    Set: TYPE ~ Sets.Set;
    nilSet: Set ~ Sets.nilSet;
    VarSet: TYPE ~ Sets.VarSet;
    ConstSet: TYPE ~ Sets.ConstSet;
    ConstFilter: TYPE ~ Sets.ConstFilter;
    BiRel: TYPE ~ BiRels.BiRel;
    nilBiRel: BiRel ~ BiRels.nilBiRel;
    RefBiRel: TYPE ~ BiRels.RefBiRel;
    VarBiRel: TYPE ~ BiRels.VarBiRel;
    ConstBiRel: TYPE ~ BiRels.ConstBiRel;
    Fn: TYPE ~ BiRels.Function;
    VarFn: TYPE ~ BiRels.VarFunction;
    UWFn: TYPE ~ BiRels.UWFunction;
    ConstFn: TYPE ~ BiRels.ConstFunction;
    InvFn: TYPE ~ BiRels.InvFunction;
    OneToOne: TYPE ~ BiRels.OneToOne;
    VarOneToOne: TYPE ~ BiRels.VarOneToOne;
    ConstOneToOne: TYPE ~ BiRels.ConstOneToOne;
    IntFn: TYPE ~ BiRels.IntFn;
    Permutation: TYPE ~ BiRels.Permutation;

    R: PROC [r: ROPE] RETURNS [ROPE] ~ INLINE {RETURN [r]};

    AV: PROC [a: REF ANY] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[ra: a]]};
    IV: PROC [i: INT] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[i: i]]};
<<The Main Point>>
    Design: TYPE = REF DesignPrivate;
    DesignPrivate: TYPE = RECORD [
        eSpace: Sets.Space,
        names: Set--of ROPE--,
        cellTypes: Set--of CellType--,
        sub: Fn--Port or Wire 
        parent: Fn--Port or Wire 
        ancest: Fn--Port or Wire 
        isTop, isntTop, isAtomic, isComposite: Set--of Port or Wire--,
        cct: ARRAY PartClass OF Fn--Part 
        partses: ARRAY PartClass OF Set--of Part--,
        pws: Set--of PW--,
        parts: Set--of Part--,
        ciType: Fn--CellInstance 
        ctName: BiRel--CellType 
        arrayElt: Fn--(array) CellType 
        ];

    Cell: TYPE ~ REF ANY --actually UNION [CellType, CellInstance]--;

    CellType: TYPE = REF CellTypePrivate;
    CellTypePrivate: TYPE = RECORD [
        d: Design,
        fullName: ARRAY PartClass OF BiRel--Part 
        inheritNames: BOOL --inherit names into me now, or later?--,
        asu: Unorganized _ NIL,
        asArray: Array _ NIL,
        asTrans: Transistor _ NIL,
        color: Color _ noColor];

    Unorganized: TYPE ~ REF UnorganizedPrivate;
    UnorganizedPrivate: TYPE ~ RECORD [
        exports: Fn--Port 
        publics, exportable, publicOrExportable, stuck: Set--of Wire-- _ nilSet
        ];

    PartClass: TYPE ~ {p, w, i};
    PWClass: TYPE ~ PartClass[p..w];
    VertexClass: TYPE ~ PartClass[w..i];

    Part: TYPE ~ REF ANY --UNION [Port, Wire, CellInstance]--;
    PW: TYPE ~ REF ANY --UNION [Port, Wire]--;

    Port: TYPE = REF PortPrivate;
    PortPrivate: TYPE = RECORD [
        color: Color _ noColor];

    Wire: TYPE = REF w VertexPrivate;
    CellInstance: TYPE = REF i VertexPrivate;
    Vertex: TYPE = REF VertexPrivate;
    VertexPrivate: TYPE = RECORD [
        QNext: Vertex _ notInQ,
        colorNext, equiv: Vertex _ NIL,
        oldColor, curColor: Color _ noColor,
        graph: GraphID _ Unspecified,
        unique, suspect: BOOL _ FALSE,
        variant: SELECT class: VertexClass FROM
            i => [
                conns: Fn--Port 
                ],
            w => [
                conns: BiRel--Port 
                ],
            ENDCASE];

    ClassOfPart: PROC [Part] RETURNS [PartClass];

    PCct: PROC [d: Design, p: Port] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.cct[p].ApplyA[p].MA]]};
    WCct: PROC [d: Design, w: Wire] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.cct[w].ApplyA[w].MA]]};
    CiCct: PROC [d: Design, ci: CellInstance] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.cct[i].ApplyA[ci].MA]]};
    VCct: PROC [d: Design, v: Vertex] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.cct[v.class].ApplyA[v].MA]]};
    PartCct: PROC [d: Design, class: PartClass, part: Part] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.cct[class].ApplyA[part].MA]]};
    CiT: PROC [d: Design, ci: CellInstance] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.ciType.ApplyA[ci].MA]]};

    Parenthood: TYPE ~ RECORD [parent: PW, index: LNAT];

    PParent: PROC [d: Design, p: Port] RETURNS [Port]
        ~ INLINE {RETURN [NARROW[d.parent.ApplyA[p].MDA]]};
    WParent: PROC [d: Design, w: Wire] RETURNS [Wire]
        ~ INLINE {RETURN [NARROW[d.parent.ApplyA[w].MDA]]};
    Top: PROC [d: Design, x: PW] RETURNS [BOOL]
        ~ INLINE {RETURN [NOT d.parent.ApplyA[x].found]};
    Atomic: PROC [d: Design, x: PW] RETURNS [BOOL]
        ~ INLINE {RETURN [NOT d.sub.HasMapA[x]]};
    Width: PROC [d: Design, x: PW] RETURNS [NATURAL]
        ~ INLINE {kids: Seq ~ BiRels.DeRef[d.sub.ApplyA[x].MA]; RETURN [kids.Size.EN]};
    Sub: PROC [d: Design, x: PW, i: LNAT] RETURNS [PW];
    PIndex: PROC [d: Design, ep: Port, parent: Port _ NIL] RETURNS [LNAT];
    WIndex: PROC [d: Design, ew: Wire, parent: Wire _ NIL] RETURNS [LNAT];
    PParenthood: PROC [d: Design, p: Port] RETURNS [Parenthood];
    WParenthood: PROC [d: Design, w: Wire] RETURNS [Parenthood];
    SubSeq: PROC [d: Design, parent: PW] RETURNS [Seq--of child--]
        ~ INLINE {RETURN BiRels.DeRef[d.sub.ApplyA[parent].MDA]};
    SubseqIndex: PROC [d: Design, kids: Seq] RETURNS [SubsIndex];
        SubsIndex: TYPE ~ RECORD [parent: PW, multiparents, sub, full: BOOL, offset: INTEGER];
    ExportableKids: PROC [ct: CellType, kids: Seq--of Wire--] RETURNS [BOOL];
    PWIsAncestor: PROC [d: Design, ancestor, descendant: PW] RETURNS [BOOL]
        ~ INLINE {RETURN [d.ancest.HasAA[descendant, ancestor]]};
    TopParts: PROC [ct: CellType, class: PWClass] RETURNS [Set];
    EnumCTParts: PROC [ct: CellType, class: PartClass, atomic, composite: BOOL, Consume: PROC [Part]];
    PWDescendants: PROC [d: Design, x: PW] RETURNS [Set]
        ~ INLINE {RETURN [d.ancest.MappingA[x, rightToLeft]]};
    NonPublicDescendants: PROC [ct: CellType, w: Wire] RETURNS [Set];
    Subcells: PROC [ct: CellType] RETURNS [Set--of CellInstance--];
    CTParts: PROC [ct: CellType, class: PartClass] RETURNS [Set];
    TypeSites: PROC [ct: CellType] RETURNS [Set--of Cell--];
    SiteConns: PROC [site: Cell] RETURNS [conns: Fn--Port 

    ConndWire: PROC [c: Cell, p: Port] RETURNS [Wire];
    AConndPort: PROC [c: Cell, w: Wire] RETURNS [Port];
    EnumerateUses: PROC [ct: CellType, Consume: PROC [CellUse]];
        CellUse: TYPE ~ REF ANY --UNION [CellInstance, (array)CellType]--;

    NFetchCellType: PROC [d: Design, name: ROPE] RETURNS [CellType];
    FetchCellType: PROC [d: Design, name: ROPE] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[d.ctName.InvApplyA[name].MDA]]};
    FetchPort: PROC [ct: CellType, fullName: SteppyName] RETURNS [Port]
        ~ INLINE {RETURN [NARROW[ct.fullName[p].InvApply[SnV[fullName]].MDA]]};
    FetchWire: PROC [ct: CellType, fullName: SteppyName] RETURNS [Wire]
        ~ INLINE {RETURN [NARROW[ct.fullName[w].InvApply[SnV[fullName]].MDA]]};
    FetchSubcell: PROC [ct: CellType, fullName: SteppyName] RETURNS [CellInstance]
        ~ INLINE {RETURN [NARROW[ct.fullName[i].InvApply[SnV[fullName]].MDA]]};

    CTNames: PROC [d: Design, ct: CellType] RETURNS [Set]
        ~ INLINE {RETURN d.ctName.MappingA[ct]};
    PNames: PROC [ct: CellType, p: Port] RETURNS [Set]
        ~ INLINE {RETURN ct.fullName[p].MappingA[p]};
    WNames: PROC [ct: CellType, w: Wire] RETURNS [Set]
        ~ INLINE {RETURN ct.fullName[w].MappingA[w]};
    INames: PROC [ct: CellType, ci: CellInstance] RETURNS [Set]
        ~ INLINE {RETURN ct.fullName[i].MappingA[ci]};
    PartNames: PROC [ct: CellType, class: PartClass, part: Part] RETURNS [Set]
        ~ INLINE {RETURN ct.fullName[class].MappingA[part]};

    ACtName: PROC [ct: CellType] RETURNS [ROPE];
    BestPName: PROC [ct: CellType, p: Port] RETURNS [SteppyName];
    BestWName: PROC [ct: CellType, w: Wire] RETURNS [SteppyName];
    BestIName: PROC [ct: CellType, ci: CellInstance] RETURNS [SteppyName];
    BestVName: PROC [ct: CellType, v: Vertex] RETURNS [SteppyName];

    PartClassName: ARRAY PartClass OF ROPE;
<<Arrays>>
    <<We make a simplifying assumption (AASEU: (Assertion about Arrays - Static Edges Uniform)): in any given wire tree in an array, 
    all wires have the same number of connections.  In other words, the connectivity of the root tells the whole story.  Because of 
    this, we can say some static edges are top, and the others are wholly owned subsidiaries.>>
    <<We also maintain AAMW: (Maximal Wires) we keep static edges and dumb wires as "high" as meaningful and possible.>>

    Array: TYPE = REF ArrayPrivate;
    ArrayPrivate: TYPE = RECORD [
        size2: Int2 _ ALL[1],
        size: NATURAL _ 1,
        basePeriod: Int2 _ ALL[1],
        buildPhase: {buildingStatrep, statrepFixed} _ buildingStatrep,
        dumrep: DumRep _ NIL,
        statrep: StatRep _ NIL
        ];

    StatRep: TYPE ~ REF StatRepPrivate;
    StatRepPrivate: TYPE ~ RECORD [
        edgeSpace, paiSpace, svSpace: Sets.Space,
        edges: Set--of StatEdge--,
            <<false: AAASEP: all StatEdges explicitly present.>>
            <<true: AAOTSE: only top stat edges are explicitly present.>>
        portEdge: ARRAY BOOL OF InvFn--elt port _ StatEdge--,
        apToPAI: Fn--array port 
        ];

    StatEdge: TYPE ~ REF StatEdgePrivate;
    StatEdgePrivate: TYPE ~ RECORD [
        vs: ARRAY BOOL OF StatVertex,
        
        <<>>

    StatVertex: TYPE ~ RECORD [port: Port, phase: Int2];
    PortAtIndex: TYPE ~ RECORD [port: Port, ai: Int2];

    DumRep: TYPE ~ REF DumRepPrivate;
    DumRepPrivate: TYPE ~ RECORD [
        dwSpace: Sets.Space,
        wires: Set--of DumbWire--,
        epToWire: Fn--elt port 
        apToWire: Fn--array port 
        ];

    DumbWire: TYPE ~ REF DumbWirePrivate;
    DumbWirePrivate: TYPE ~ RECORD [
        eps: BiRel--elt port 
        children: Seq--of DumbWire-- _ nilBiRel,
        parent: DumbWire _ NIL, index: LNAT _ LNAT.LAST];

    TopDumbWire: TYPE ~ DumbWire --with parent=NIL--;
    ChildDumbWire: TYPE ~ DumbWire --with parent#NIL--;

    CompositeArrayIndex: TYPE ~ NATURAL;

    ComposeAI: PROC [a: Array, ai: Int2] RETURNS [CompositeArrayIndex]
        ~ INLINE {RETURN [a.size2[Y]*ai[X]+ai[Y]]};

    DecomposeAI: PROC [a: Array, cai: CompositeArrayIndex] RETURNS [ai: Int2]
        ~ INLINE {ai[X] _ cai/a.size2[Y]; ai[Y] _ cai - ai[X]*a.size2[Y]};

    EltType: PROC [act: CellType] RETURNS [CellType]
        ~ INLINE {RETURN [NARROW[act.d.arrayElt.ApplyA[act].MA]]};

    ArrayEltPortsConnected: PROC [act: CellType, ai1, ai2: Int2, ep1, ep2: Port] RETURNS [BOOL];

    SomePAI: PROC [act: CellType, dw: DumbWire] RETURNS [PortAtIndex];

    SvV: PROC [sv: StatVertex] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[ra: sv.port, i: LOOPHOLE[sv.phase]]]};

    VSv: PROC [v: Sets.Value] RETURNS [StatVertex]
        ~ INLINE {RETURN [[port: NARROW[v.ra], phase: LOOPHOLE[v.i]]]};

    PaiV: PROC [pai: PortAtIndex] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[ra: pai.port, i: LOOPHOLE[pai.ai]]]};

    VPai: PROC [v: Sets.Value] RETURNS [PortAtIndex]
        ~ INLINE {RETURN [[port: NARROW[v.ra], ai: LOOPHOLE[v.i]]]};

    I2V: PROC [x: Int2] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[ra: NIL, i: LOOPHOLE[x]]]};

    VI2: PROC [v: Sets.Value] RETURNS [Int2]
        ~ INLINE {RETURN LOOPHOLE[v.i]};
<<Transistors>>
    <<Uh, yuk.>>

    Transistor: TYPE = REF TransistorPrivate;
    TransistorPrivate: TYPE = RECORD [
        type: ROPE,
        length, width, area, perimeter: LNAT _ 0
        ];
<<General Naming>>
    Describe: PROC [d: Design, subject: REF ANY, relativeTo: REF ANY _ NIL, nameGen: NameGenerator _ NIL] RETURNS [ROPE];

    SteppyDescribe: PROC [d: Design, subject: REF ANY, relativeTo: REF ANY _ NIL, nameGen: NameGenerator _ NIL] RETURNS [SteppyName];

    NameGenerator: TYPE = REF NameGeneratorPrivate;
    NameGeneratorPrivate: TYPE = RECORD [
        GenerateName: PROC [data, subject: REF ANY] RETURNS [ROPE],
        data: REF ANY _ NIL
        ];

    RelativeNames: PROC [ct: CellType, class: PWClass, anc, des: PW] RETURNS [Set--of SteppyName--];
    ScanRelativeNames: PROC [ct: CellType, class: PWClass, anc, des: PW, Test: PROC [SteppyName] RETURNS [BOOL]] RETURNS 
    [MaybeSteppyName];
    AcceptAnySteppyName: PROC [SteppyName] RETURNS [BOOL];
<<Steppy (Structured) Names>>
    SteppyNameList: TYPE ~ LIST OF SteppyName;
    MaybeSteppyName: TYPE ~ RECORD [found: BOOL, it: SteppyName];
    SteppyName: TYPE ~ RECORD [
        steps: NameStepList,
        grade: SteppyNameGrade];

    NameStepList: TYPE ~ LIST OF NameStep --most significant first--;
    NameStep: TYPE ~ REF ANY --actually UNION [ROPE, REF INT]--;

    SteppyNameGrade: TYPE ~ RECORD [
        global: BOOL,
        nonsubs: NATURAL,
        gend: BOOL,
        subs: NATURAL];

    noGrade: SteppyNameGrade ~ [FALSE, 0, FALSE, 0];
    noName: SteppyName ~ [NIL, noGrade];
    noNameVal: Sets.Value ~ [NIL, LOOPHOLE[noGrade]];

    SnV: PROC [sn: SteppyName] RETURNS [Sets.Value]
        ~ INLINE {RETURN [[ra: sn.steps, i: LOOPHOLE[sn.grade]]]};

    VSn: PROC [v: Sets.Value] RETURNS [SteppyName]
        ~ INLINE {RETURN [[steps: NARROW[v.ra], grade: LOOPHOLE[v.i]]]};

    LSn: PROC [NameStepList] RETURNS [SteppyName];

    OSn: PROC [ns: NameStep] RETURNS [SteppyName]
        ~ INLINE {RETURN LSn[LIST[ns]]};

    ListRopes: PROC [LOR] RETURNS [Set--of ROPE--];

    OneRope: PROC [r: ROPE] RETURNS [Set--of ROPE--]
        ~ INLINE {RETURN [Sets.CreateSingleA[r, SetBasics.ropes[TRUE]]]};

    ListSteppys: PROC [SteppyNameList] RETURNS [Set--of SteppyName--];

    OneSteppy: PROC [sn: SteppyName] RETURNS [Set--of SteppyName--]
        ~ INLINE {RETURN [Sets.CreateSingleton[SnV[sn], steppyNameSpace]]};

    OneLSn: PROC [ns: NameStep] RETURNS [Set--of SteppyName--]
        ~ INLINE {RETURN OneSteppy[OSn[ns]]};

    ParseSteppyName: PROC [raw: ROPE] RETURNS [SteppyName];
    UnparseSteppyName: PROC [s: SteppyName] RETURNS [ROPE];

    ActualName: PROC [cin, pn: SteppyName] RETURNS [SteppyName];
    ActualNames: PROC [cins, pns: Set--of SteppyName--] RETURNS [Set];
    SNsCat: PROC [as, bs: Set--of SteppyName--] RETURNS [Set--of SteppyName--];
    SNCat: PROC [a, b: SteppyName] RETURNS [SteppyName];
    SNPrepend: PROC [NameStep, SteppyName] RETURNS [SteppyName];
    SNAppend: PROC [SteppyName, NameStep] RETURNS [SteppyName];
    SteppyIsPrefix: PROC [prefix, full: SteppyName] RETURNS [MaybeSteppyName];
    SteppyIsSuffix: PROC [suffix, full: SteppyName] RETURNS [MaybeSteppyName];

    AIName: PROC [act: CellType, ai: Int2] RETURNS [SteppyName];

    SteppyNameGradeCompare: PROC [g1, g2: SteppyNameGrade] RETURNS [SetBasics.TotalComparison];
    NameStepListCompare: PROC [l1, l2: NameStepList] RETURNS [SetBasics.TotalComparison];
    NameStepListEqual: PROC [l1, l2: NameStepList, clip1, clip2: NameStepList _ NIL] RETURNS [BOOL];

    nameStepSpace, steppyNameSpace: READONLY Sets.Space;
    emptyRopeSet, emptySteppySet: READONLY Set;
    intVsNs: READONLY OneToOne;
<<Circuit Graph Stuff>>
    GraphID: TYPE = {A, B, Unspecified};
    RealGraphID: TYPE = GraphID[A .. B];
    OtherGraph: ARRAY RealGraphID OF RealGraphID = [A: B, B: A];
    graphIDToRope: GraphDescriptions;
    GraphDescriptions: TYPE ~ ARRAY GraphID OF ROPE;
    RealGraphDescriptions: TYPE ~ ARRAY RealGraphID OF ROPE;
    Color: TYPE = INT;
    noColor: Color = LAST[Color];
    someColor: Color = 87654321H;

    FilterColor: PROC [color: Color] RETURNS [filtered: Color] = INLINE {
        filtered _ IF color # noColor THEN color ELSE someColor};

    notInQ: Vertex --don't look:-- = NIL --you looked!--;
    endOfQ: READONLY Vertex;
<<Head&Tail Lists>>
    TList: TYPE ~ RECORD [head, tail: LORA _ NIL];

    Cat: PROC [a, b: TList] RETURNS [TList]
        ~ INLINE {IF a.head=NIL THEN RETURN [b] ELSE IF b.head=NIL THEN RETURN [a] ELSE {a.tail.rest _ b.head; RETURN [[a.head, b.tail]]}};
    Prepend: PROC [l: TList, ra: REF ANY] RETURNS [l2: TList]
        ~ INLINE {l2.head _ CONS[ra, l.head]; l2.tail _ IF l.tail#NIL THEN l.tail ELSE l2.head};
    Append: PROC [l: TList, ra: REF ANY] RETURNS [l2: TList]
        ~ INLINE {l2.tail _ LIST[ra]; IF l.head=NIL THEN l2.head _ l2.tail ELSE {l2.head _ l.head; l.tail.rest _ l2.tail}};
    CopyTil: PROC [TList] RETURNS [TList];
<<Randumb conveniences>>
    Seq: TYPE ~ BiRels.Sequence;

    CreateSeq: PROC [len: NATURAL _ 0, oneToOne, dense, domainFixed: BOOL _ FALSE, rightSpace: Sets.Space _ SetBasics.refs] RETURNS 
    [Seq]
        ~ INLINE {RETURN [BiRels.CreateVector[bounds: [0, len-1], val: Sets.noValue, oneToOne: oneToOne, dense: dense, domainFixed: 
        domainFixed, rightSpace: rightSpace]]};

    NewInt: PROC [i: INT] RETURNS [REF INT];
        <<Treat the result as a REF READONLY INT, or you'll be sorry!>>

    FloorDiv: PROC [num, den: INT] RETURNS [INT] ~ INLINE {
        IF den<0 THEN {num _ -num; den _ -den};
        RETURN [IF num>=0 THEN (num/den) ELSE ((num-den+1)/den)]};
    CeilDiv: PROC [num, den: INT] RETURNS [INT] ~ INLINE {
        IF den<0 THEN {num _ -num; den _ -den};
        RETURN [IF num>=0 THEN ((num+den-1)/den) ELSE (num/den)]};

    ExtendName: PROC [fileName, defaultExtension: ROPE] RETURNS [fullFName: ROPE, cp: FS.ComponentPositions];
END.