[Cyan]<DATools7.0>Lichen2>LichenDataOps.Mesa!8

LichenDataOps.Mesa

Last tweaked by Mike Spreitzer on May 6, 1988 9:56:10 am PDT

DIRECTORY IO, AbSets, LichenDataStructure;

LichenDataOps: CEDAR DEFINITIONS

IMPORTS LichenDataStructure

BEGIN OPEN Sets:AbSets, LichenDataStructure;

CreateDesign: PROC [names: Set--of ROPE--] RETURNS [Design];

CellFlavor: TYPE ~ {leaf, unorganized, array};

CreateCellType: PROC [d: Design, flavor: CellFlavor, names: Set--of ROPE--] RETURNS [CellType];

CreateArray: PROC [d: Design, eltType: CellType, size, basePeriod: Int2, names: Set--of ROPE--] RETURNS [CellType];

FinishedMakingArrayConnections: PROC [act: CellType];

CreatePort: PROC [ct: CellType, fullNames: Set--of SteppyName--, addum, fixExpConns, fixInstConns, fixWExpConns, fixWInstConns: BOOL, children: Seq--of Port-- ← nilBiRel] RETURNS [Port];

Dummy wires are added iff addum; fixWExpConns and fixWInstConns tell whether to fix up connections to the dummies.

CreateWire: PROC [ct: CellType, fullNames: Set--of SteppyName--, fixExpConns, fixInstConns: BOOL, children: Seq--of Wire-- ← nilBiRel] RETURNS [Wire];

Instantiate: PROC [ict, cct: CellType, addum: BOOL, names: Set--of SteppyName--] RETURNS [CellInstance];

KnowVertexName: PROC [d: Design, v: Vertex, fullName: SteppyName]

~ INLINE {KnowVertexNames[d, v, OneSteppy[fullName]]};

KnowVertexNames: PROC [d: Design, v: Vertex, fullNames: Set--of SteppyName--];

KnowPortName: PROC [d: Design, p: Port, fullName: SteppyName]

~ INLINE {KnowPortNames[d, p, OneSteppy[fullName]]};

KnowPortNames: PROC [d: Design, p: Port, fullNames: Set--of SteppyName--];

ForgetVertexName: PROC [d: Design, v: Vertex, fullName: SteppyName];

ForgetPortName: PROC [d: Design, p: Port, fullName: SteppyName];

PortForWire: PROC [ct: CellType, internal: Wire, mayAdd: BOOL] RETURNS [port: Port];

FullySfwdlyExportWires: PROC [ct: CellType, wires: Set];

GetArrayPortForPort: PROC [act: CellType, ai: Int2, ep: Port, mayAdd: BOOL] RETURNS [arrayPort: Port];

Connect: PROC [d: Design, wire: Wire, port: Port, site: Cell];

MakeArrayNewConnection: PROC [act: CellType, rangeA: Range2, delta: Int2, epA, epB: Port];

NoteNewEltPort: PROC [act: CellType, ep: Port];

NoteNewArrayPort: PROC [act: CellType, ap: Port];

MergeNets: PROC [d: Design, w1, w2: Wire] RETURNS [merged, deleted: Wire];

May only be invoked on private top atomic wires.

AddDeducedStructureToDesign: PUBLIC PROC [design: Design, pacify: IO.STREAM ← NIL];

DeduceStructureForWires: PROC [ct: CellType, pacify: IO.STREAM ← NIL] RETURNS [new: Set--of Wire--];

DeduceStructureForPorts: PROC [ct: CellType, pacify: IO.STREAM ← NIL] RETURNS [new: Set--of Port--];

PrefixifyDesign: PROC [Design];

InheritNames: PUBLIC PROC [design: Design];

END.