<> <> DIRECTORY IO, AbSets, LichenDataStructure; LichenDataOps: CEDAR DEFINITIONS = BEGIN OPEN Sets:AbSets, LichenDataStructure; CreateDesign: PROC [names: Set--of ROPE--] RETURNS [Design]; CellFlavor: TYPE ~ {leaf, unorganized, array}; CreateCellType: PROC [d: Design, flavor: CellFlavor, bbox: Range2, names: Set--of ROPE--] RETURNS [CellType]; FinishCreatingUnorganized: PROC [ct: CellType]; CreateArray: PROC [d: Design, eltType: CellType, size, basePeriod: Int2, Set--of ROPE--] RETURNS [CellType]; CreateArrayPart: PROC [act, ect: CellType, size, basePeriod: Int2, SetArrayPart: PROC [act, ect: CellType, a: Array]; TrimStatrep: PROC [act: CellType, a: Array, edges: Set--of StatEdge-- _ nilSet]; FinishedMakingArrayConnections: PROC [act: CellType]; ForgetUnorganized: PROC [ct: CellType]; ForgetArray: PROC [CellType]; OffsetsFromList: PROC [OffsetPatList] RETURNS [OffsetSeq]; OffsetPatList: TYPE ~ LIST OF OffsetPat; CTIncludesPoint: PROC [CellType, Int2]; DesignScaleIs: PROC [Design, REAL]; CreatePort: PROC [ct: CellType, fullNames: Set--of SteppyName--, deduced, addum, nameDum, fixExpConns, fixInstConns, fixWExpConns, fixWInstConns: BOOL, children: Seq--of Port-- _ nilBiRel] RETURNS [Port]; <> CreateWire: PROC [ct: CellType, fullNames: Set--of SteppyName--, deduced, fixExpConns, fixInstConns: BOOL, children: Seq--of Wire-- _ nilBiRel] RETURNS [Wire]; Instantiate: PROC [ict, cct: CellType, addum: BOOL, xfm: Transform, offset: Int2, names: Set--of SteppyName--] RETURNS [CellInstance]; KnowPartName: PROC [ct: CellType, class: PartClass, part: Part, fullName: SteppyName, onlyIfGood: BOOL]; KnowPartNames: PROC [ct: CellType, class: PartClass, part: Part, fullNames: Set--of SteppyName--, onlyIfGood: BOOL]; ForgetPartName: PROC [ct: CellType, class: PartClass, part: Part, fullName: SteppyName]; ForgetPartNames: PROC [ct: CellType, class: PartClass, part: Part, fullNames: Set]; ReplaceDescendantsName: PROC [ct: CellType, subroot: PW, old, new: SteppyName]; ReplaceDescendantsNames: PROC [ct: CellType, subroot: PW, oldNew: BiRel--old SteppyName KnowVertexName: PROC [ct: CellType, v: Vertex, fullName: SteppyName, onlyIfGood: BOOL] ~ INLINE {KnowPartName[ct, v.class, v, fullName, onlyIfGood]}; KnowVertexNames: PROC [ct: CellType, v: Vertex, fullNames: Set--of SteppyName--, onlyIfGood: BOOL] ~ INLINE {KnowPartNames[ct, v.class, v, fullNames, onlyIfGood]}; ForgetVertexName: PROC [ct: CellType, v: Vertex, fullName: SteppyName] ~ INLINE {ForgetPartName[ct, v.class, v, fullName]}; KnowPortName: PROC [ct: CellType, p: Port, fullName: SteppyName, onlyIfGood: BOOL] ~ INLINE {KnowPartName[ct, p, p, fullName, onlyIfGood]}; KnowPortNames: PROC [ct: CellType, p: Port, fullNames: Set--of SteppyName--, onlyIfGood: BOOL] ~ INLINE {KnowPartNames[ct, p, p, fullNames, onlyIfGood]}; ForgetPortName: PROC [ct: CellType, p: Port, fullName: SteppyName] ~ INLINE {ForgetPartName[ct, p, p, fullName]}; PortForWire: PROC [ct: CellType, internal: Wire, mayAdd: BOOL] RETURNS [port: Port]; FullySfwdlyExportWires: PROC [ct: CellType, wires: Set] RETURNS [Set--of Port--]; GetArrayPortForPort: PROC [act: CellType, ai: Int2, ep: Port, mayAdd, addum, nameDum: BOOL] RETURNS [arrayPort: Port]; <<>> Connect: PROC [d: Design, wire: Wire, port: Port, site: Cell]; ConnectPWs: PROC [d: Design, pws: Fn, site: Cell]; ConnectPCs: PROC [d: Design, wire: Wire, pcs: BiRel]; ClosePortConnectivity: PROC [d: Design, parent: Port, kidPorts: Seq--of Port--, conns: Fn--Port ClosePortsConnectivity: PROC [d: Design, parents: Set--of Port--, conns: Fn--Port MakeArrayNewConnection: PROC [d: Design, a: Array, rangeA: Range2, delta: Int2, epA, epB: Port]; MakeArrayConnectionAtPhase: PROC [d: Design, a: Array, rangeA: Range2, MakeArrayExport: PROC [d: Design, a: Array, ap, ep: Port, ai: Int2]; NoteNewEltPort: PROC [act: CellType, ep: Port]; NoteNewArrayPort: PROC [act: CellType, ap: Port]; NoteExEltPorts: PROC [ect: CellType, eps: Set--of port--, mayHaveConsequences: BOOL, log: IO.STREAM _ NIL]; NoteEltPortMerge: PROC [ect: CellType, kept: Port, lost: Set--of port--]; MayDeletePorts: PROC [ct: CellType, ports: Set--of port--, timid, isWholeTrees: BOOL] RETURNS [whyNot: ROPE]; TryToMergeDumbWires: PROC [d: Design, act: CellType, wires: Set] RETURNS [balks: Set--of DumbWire--]; <> MergeNets: PROC [d: Design, w1, w2: Wire, callerWillTakeCareOfPorts: BOOL] RETURNS [merged, deleted: Wire]; <> <> MergeWireSet: PROC [d: Design, wires: Set, callerWillTakeCareOfPorts: BOOL] RETURNS [kept: Wire, lost: Set]; <> MergePorts: PROC [ct: CellType, ports: Set] RETURNS [kept: Port, lost: Set]; <> MergeCellTypes: PROC [d: Design, lost, kept: CellType, assoc: OneToOne]; <> DeleteWires: PROC [ct: CellType, wires: Set, visitConns: BOOL]; <> DeletePorts: PROC [ct: CellType, ports: Set, visitInsts, deleteWires: BOOL, log: IO.STREAM _ NIL]; <> DeleteInsts: PROC [d: Design, cis: Set, visitWires: BOOL]; DeleteCellType: PROC [ct: CellType, log: IO.STREAM]; Differentiate: PROC [d: Design, cis: Set] RETURNS [new: CellType]; FixInterleavingsOfArray: PROC [act: CellType]; AddDeducedStructureToDesign: PUBLIC PROC [design: Design, pacify: IO.STREAM _ NIL]; DeduceStructureForWires: PROC [ct: CellType, pacify: IO.STREAM _ NIL] RETURNS [new: Set--of Wire--]; DeduceStructureForPorts: PROC [ct: CellType, pacify: IO.STREAM _ NIL] RETURNS [new: Set--of Port--]; PrefixifyDesign: PROC [Design]; DropPhysical: PROC [d: Design]; CreateBareWire: PROC [Design] RETURNS [Wire]; CreateBareInstance: PROC [d: Design, offset: Int2] RETURNS [CellInstance]; CreateBareDumbWire: PROC [act: CellType] RETURNS [DumbWire]; CreateDumbWireKids: PROC [a: Array, len: LNAT] RETURNS [Seq--of DumbWire--]; ExpandType: PROC [d: Design, ct: CellType]; ExpandInstance: PROC [d: Design, ci: CellInstance]; UnorganizeArray: PROC [CellType]; END.