DIRECTORY FS, IO, Collections, LichenDataStructure; LichenDataOps: CEDAR DEFINITIONS = BEGIN OPEN Colls:Collections, LichenDataStructure; EnsureAllIn: PROC [design: Design]; EnsurePublic: PROC [ct: CellType]; EnsurePrivate: PROC [ct: CellType]; ExpansionKnown: PROC [ct: CellType] RETURNS [known: BOOL]; AssertionOp: TYPE = {ignore, report, check, establish}; MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check]; FailableAssertionOp: TYPE = AssertionOp [report .. check]; CheckDesign: PROC [design: Design, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp]; CheckCellType: PROC [ct: CellType, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; CheckCellTypes: PROC [cts: ConstSet--of CellType--, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; NoteChange: PROC [cellType: CellType]; AddPort: PROC [p: PortPrivate _ []] RETURNS [port: Port]; FullyAddPort: PROC [p: PortPrivate _ [], andReportConnectionTo: CellInstance _ NIL] RETURNS [port: Port, connection: Wire _ NIL]; RemovePort: PROC [port: Port]; AddEdge: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; AddEdges: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; RemoveEdge: PROC [e: Edge]; RemoveEdges: PROC [e: Edge]; UnlinkPort: PROC [ci: CellInstance, port: Port]; UnlinkPorts: PROC [ci: CellInstance, ports: ConstSet--of Port--]; Instantiate: PROC [type, containingCT: CellType, names: ListData _ NIL, other: Assertions _ NIL] RETURNS [ci: CellInstance]; PortForWire: PROC [ct: CellType, internal: Wire, ci: CellInstance, mayAdd: BOOL] RETURNS [port: Port, external: Wire]; FullyInstantiate: PROC [type, containingCT: CellType, names: ListData _ NIL, other: Assertions _ NIL] RETURNS [ci: CellInstance]; CreateWire: PROC [containingCT: CellType, containingWire: Wire _ NIL, names: ListData _ NIL, other: Assertions _ NIL, copy: Wire _ NIL] RETURNS [w: Wire]; CreateIntermediary: PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, names: ListData _ NIL, other: Assertions _ NIL] RETURNS [im: Intermediary]; CreateCellType: PROC [design: Design, cellTypeName: ROPE, class: CellClass, internals: BOOL, otherPublic, otherPrivate: Assertions _ NIL] RETURNS [ct: CellType]; CreateArray: PROC [design: Design, cellTypeName: ROPE, class: CellClass, eltType: CellType, size, jointsPeriod: Size2, borders: ARRAY Dim OF ARRAY End OF NAT, otherPublic, otherPrivate: Assertions _ NIL] RETURNS [ct: CellType]; KnowVertexName: PROC [v: Vertex, name: SteppyName]; ForgetVertexName: PROC [v: Vertex, name: SteppyName]; IndexVertexNames: PROC [v: Vertex, names: Set _ Colls.nilColl]; UnindexVertexNames: PROC [v: Vertex]; NoteLevelChange: PROC [w: Wire]; DeleteVertex: PROC [v: Vertex]; IsMirror: PROC [v: CellInstance] RETURNS [isMirror: BOOL]; AddMirror: PROC [CellType]; MergeNets: PROC [net1, net2: Wire] RETURNS [merged, doomed: Wire]; GroupWires: PROC [sibs: Seq--of wire--, parentNames: ListData] RETURNS [parent: Wire]; GroupPorts: PROC [sibs: Seq--of port--, parentNames: ListData] RETURNS [parent: Port]; ExpandName: PROC [fileName, defaultExtension: ROPE] RETURNS [fullFName: ROPE, cp: FS.ComponentPositions]; ParseSteppyName: PROC [raw: ROPE] RETURNS [p: SteppyName]; UnparseSteppyName: PROC [s: SteppyName] RETURNS [ROPE]; Log: PROC [fmt: ROPE, args: LORA _ NIL]; PrintOnLog: PROC [REF ANY]; END. ΠLichenDataOps.Mesa Last tweaked by Mike Spreitzer on August 27, 1987 2:17:23 pm PDT = A ct B deisgn : EnsurePrivate[ct] Make sure interface is fully defined. Make sure the internals are as known as possible. Do we know how this cell type is decomposed? Adds as last child of parent, if any. Adds dummy wires by instances and groups in arrays. Edge for port.prev (if that's not NIL) must already be present. Will introduce Intermediaries, if necessary. Removes ancestor Intermediaries that have no children. Remove the edge for given port, which must be immediately connected. Remove the edges for given ports, which need not be immediately connected. If ci#NIL, ci.port is connected to external. Adds dummy wires. As last child of containingWire, if any. With same structure as copy, if given, leaf structure otherwise. The sibs must all be siblings; the parent is introduced in their place and the siblings are moved below the parent. Graph connections are fixed up. Κ(– "cedar" style˜code™K™@—K˜KšΟk œœœ#˜3K˜šΠbx œœ œ˜"K˜KšœœΟnœ"˜2K˜šŸ œœ˜#KšœΟmœ œ™#—K˜šŸ œœ˜"K™%—K˜šŸ œœ˜#K™1—K˜šŸœœœ œ˜:K™,—K˜Kšœ œ&˜7Kšœœ!˜AKšœœ!˜:K˜KšŸ œœR˜cKšŸ œœqœœ˜‘Kš ŸœœΟcœcœœ˜’K˜KšŸ œœ˜&K˜šŸœœœ˜9K™%—š Ÿ œœ=œœ!œ˜K™3—KšŸ œœ˜šŸœœœœ˜?K™?—šŸœœœœ˜@K™,—KšŸ œœ ˜šŸ œœ ˜K™6—šŸ œœ ˜0K™D—šŸ œœ#‘ œ˜AK™J—Kš Ÿ œœ2œœœ˜|šŸ œœ:œœ˜vK™,—š Ÿœœ2œœœ˜K™—šŸ œœ1œœœœœ ˜šKšœ(™(K™@—Kš ŸœœZœœœ˜«Kš Ÿœœ œœ*œœ˜‘KšŸ œœ œKœœœœœ*œœ˜γKšŸœœ˜3KšŸœœ˜5KšŸœœ)˜?KšŸœœ ˜%KšŸœœ ˜ KšŸ œœ ˜KšŸœœœ œ˜:KšŸ œœ ˜KšŸ œœœ˜BšŸ œœ ‘ œœ˜VKšœ”™”—KšŸ œœ ‘ œœ˜VK˜Kš Ÿ œœœœ œœ˜iKšŸœœœœ˜:KšŸœœœœ˜7K˜Kš Ÿœœœœœ˜(KšŸ œœœœ˜K˜Kšœ˜——…— €x