StaticTest.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Barth, November 25, 1986 3:45:55 pm PST
DIRECTORY CoreClasses, CoreCreate, CoreFlat, CoreOps, Static, TerminalIO;
StaticTest:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, Static, TerminalIO
= BEGIN
CreateInverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
ntrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Gnd]],
type: CoreClasses.CreateTransistor[[nE]]
]];
ptrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Vdd]],
type: CoreClasses.CreateTransistor[[pE]]
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
instances: LIST [ntrans, ptrans],
name: "Inverter"
];
};
Create2Inverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
Intern: CoreCreate.Wire ← CoreOps.CreateWire[name: "Intern"];
InInternOut: CoreCreate.Wire ← CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"];
inverter: CoreCreate.CellType ← CreateInverter[];
first: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]],
type: inverter
]];
second: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]],
type: inverter
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]],
instances: LIST [first, second],
name: "Inverter2"
];
};
CreateBrokeInverter2:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
InternA: CoreCreate.Wire ← CoreOps.CreateWire[name: "InternA"];
InternB: CoreCreate.Wire ← Static.UnconnectedOK[CoreOps.CreateWire[name: "InternB"]];
inverter: CoreCreate.CellType ← CreateInverter[];
first: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, InternA, Gnd, Vdd]],
type: inverter
]];
second: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [InternB, Out, Gnd, Vdd]],
type: inverter
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, InternA, InternB]],
instances: LIST [first, second],
name: "BrokeInverter2"
];
};
Test:
PROC = {
Check: Static.ConnectionCountProc = {
TerminalIO.PutRope[CoreOps.GetFullWireName[wireRoot, wire]];
TerminalIO.PutRope[IF public THEN " of cell " ELSE " in cell "];
TerminalIO.PutRope[CoreOps.GetCellTypeName[cellType]];
TerminalIO.PutF[" has %g connections\n", [integer[count]]];
};
cellType: CoreCreate.CellType ← Create2Inverter[];
cutSet: CoreFlat.CutSet ← CoreFlat.CreateCutSet[cellTypes: LIST["Inverter"]];
TerminalIO.PutRope["\n"];
Static.CountLeafConnections[cellType, Check, cutSet];
Static.CountLeafConnections[cellType, Static.CheckCount, cutSet];
TerminalIO.PutRope["\n"];
Static.CountLeafConnections[cellType, Check];
Static.CountLeafConnections[cellType, Static.CheckCount];
TerminalIO.PutRope["\n"];
cellType ← CreateBrokeInverter2[];
Static.CountDirectConnections[cellType, Static.CheckCount];
TerminalIO.PutRope["\n"];
Static.CountDirectConnections[cellType, Static.CheckCount, cutSet];
};
END.