DIRECTORY CD, CDImports, Core, CoreDirectory, PW, PWCore, Rope, Sisyph; StdCellsCmosB: CEDAR PROGRAM IMPORTS CDImports, CoreDirectory, PW, PWCore, Sisyph ~ BEGIN CellType: TYPE = Core.CellType; ROPE: TYPE = Rope.ROPE; schDesignName: ROPE = "SCLibCMOSB"; schDesign: CD.Design; schDesignCx: Sisyph.Context; libName: ROPE = "CMOSB"; -- known to the designer lib: CoreDirectory.Library; Extract: PROC [name: ROPE] RETURNS [cellType: CellType] ~ { cellType _ Sisyph.ExtractSchematicByName[name: name, cx: schDesignCx]; }; MakeSCCell: PROC [name, schName: ROPE] ~ { ct: CellType _ Extract[schName]; -- extract schematics from schDesign [] _ CoreDirectory.Insert[lib, name, ct]; -- register the cell in the library PWCore.SetGet[ct, schDesign]; -- specify the layout }; schDesign _ PW.OpenDesign[schDesignName]; [] _ CDImports.Load[into: schDesign, importeeName: "SSI"]; schDesignCx _ Sisyph.Create[schDesign, Sisyph.defaultGlobalNames]; lib _ CoreDirectory.RegisterLibrary[CoreDirectory.CreateLibrary[], libName]; MakeSCCell["gnd", "C2GD00A.sch"]; MakeSCCell["vdd", "C2VD00A.sch"]; MakeSCCell["inv", "C2IV00A.sch"]; MakeSCCell["invBuffer", "C2IV00B.sch"]; MakeSCCell["tstDriver", "C2BD02A.sch"]; MakeSCCell["and2", "C2AN02A.sch"]; MakeSCCell["and3", "C2AN03A.sch"]; MakeSCCell["and4", "C2AN04A.sch"]; MakeSCCell["nand2", "C2NA02A.sch"]; MakeSCCell["nand3", "C2NA03A.sch"]; MakeSCCell["nand4", "C2NA04A.sch"]; MakeSCCell["or2", "C2OR02A.sch"]; MakeSCCell["or3", "C2OR03A.sch"]; MakeSCCell["or4", "C2OR04A.sch"]; MakeSCCell["nor2", "C2NO02A.sch"]; MakeSCCell["nor3", "C2NO03A.sch"]; MakeSCCell["nor4", "C2NO04A.sch"]; MakeSCCell["xor2", "C2XR02A.sch"]; MakeSCCell["xnor2", "C2XN02A.sch"]; MakeSCCell["dLatch", "C2LT01A.sch"]; END. άStdCellsCmosB.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Louis Monier, July 14, 1986 1:25:29 pm PDT Last Edited by: Louis Monier July 18, 1986 9:18:30 am PDT -- Defines every cell of a standard cell library for CMosB (2m CMOS with two levels of metal, fabricated by both VTI and ICL). Will be used by the library "Logic". Layout of first cells courtesy of Christian Jacobi. As much as possible, the cells follow the terminology used in the "CMOS Standard Cell User's Guide and Data Manual" from ED (January1986, Release 2.0). Library -- The source of schematics and layout -- The library, in the sense of CoreDirectory, i.e. a collection of cellTypes Initialization Basic combinatorial cells Latches Κ!˜codešœ™Kšœ Οmœ1™