DIRECTORY Core, CoreClasses, CoreOps, IO, Rope, RopeList, SC, SCTestUtil, ViewerIO; SCTestInteriorCore: CEDAR PROGRAM IMPORTS CoreOps, RopeList, SCTestUtil, ViewerIO EXPORTS SCTestUtil = BEGIN CellType: TYPE = Core.CellType; CellInstance: TYPE = CoreClasses.CellInstance; debug: BOOL _ FALSE; FetchCell: PROC [name: Rope.ROPE, wires: LIST OF Rope.ROPE] RETURNS [CellType] = { wire: Core.Wire _ SCTestUtil.CreateWire[RopeList.Append[wires, LIST["Vdd", "Gnd"]]]; RETURN [ SCTestUtil.CreateRecordCell[name, wire, wire, NIL] ]; }; CreateCore: PUBLIC PROC [] RETURNS [CellType] = BEGIN Inst: PROC [cell: CellType, wires: LIST OF Rope.ROPE, name: Rope.ROPE] RETURNS [i: CellInstance] = { i _ SCTestUtil.CreateInstance[RopeList.Append[wires, LIST["Vdd", "Gnd"]], cell, name, allWires]; }; Short: CellType _ FetchCell["my-dummy", LIST["in", "out"]]; Inv: CellType _ FetchCell["my-C1IV00A", LIST["I", "X"]]; NAnd2: CellType _ FetchCell["my-C1NA02A", LIST["IXA", "IXB", "X"]]; NAnd3: CellType _ FetchCell["my-C1NA03A", LIST["IXA", "IXB", "IXC", "X"]]; NAnd4: CellType _ FetchCell["my-C1NA04A", LIST["IXA", "IXB", "IXC", "IXD", "X"]]; NOr2: CellType _ FetchCell["my-C1NO02A", LIST["IXA", "IXB", "X"]]; NOr3: CellType _ FetchCell["my-C1NO03A", LIST["IXA", "IXB", "IXC", "X"]]; NOr4: CellType _ FetchCell["my-C1NO04A", LIST["IXA", "IXB", "IXC", "IXD", "X"]]; And2: CellType _ FetchCell["my-C1AN02A", LIST["IXA", "IXB", "X"]]; And3: CellType _ FetchCell["my-C1AN03A", LIST["IXA", "IXB", "IXC", "X"]]; And4: CellType _ FetchCell["my-C1AN04A", LIST["IXA", "IXB", "IXC", "IXD", "X"]]; Or2: CellType _ FetchCell["DLatch", LIST["D", "S", "Q"]]; Or3: CellType _ FetchCell["my-C1OR03A", LIST["IXA", "IXB", "IXC", "X"]]; Or4: CellType _ FetchCell["my-C1OR04A", LIST["IXA", "IXB", "IXC", "IXD", "X"]]; Xor: CellType _ FetchCell["my-C1XR02A", LIST["IXA", "IXB", "X"]]; Xnor: CellType _ FetchCell["my-C1XN02A", LIST["IXA", "IXB", "X"]]; Latch1: CellType _ FetchCell["my-C1LT01A", LIST["NCK", "D", "Q", "NQ"]]; Latch2: CellType _ FetchCell["my-C1LT02A", LIST["CK", "D", "Q", "NQ"]]; Latch3: CellType _ FetchCell["my-C1LT03A", LIST["NCK", "D", "P", "Q", "NQ"]]; Latch4: CellType _ FetchCell["my-C1LT04A", LIST["NCK", "D", "R", "Q", "NQ"]]; pubWires: Core.Wire _ SCTestUtil.CreateWire[ LIST["In1", "In2", "In3", "In4", "OutDummy", "OutInv", "OutNAnd2", "OutNAnd3", "OutNAnd4", "OutNOr2", "OutNOr3", "OutNOr4", "OutOr2", "OutOr3", "OutOr4", "OutAnd2", "OutAnd3", "OutAnd4", "OutXor", "OutXnor", "OutL1Q", "OutL2Q", "OutL3Q", "OutL4Q", "OutL1NQ", "OutL2NQ", "OutL3NQ", "OutL4NQ", "Vdd", "Gnd"]]; intWires: Core.Wire _ SCTestUtil.CreateWire[LIST["In1a", "In1b", "In1c", "In1d", "In2a", "In2b", "In2c", "In2d", "In3a", "In3b", "In3c", "In3d", "In4a", "In4b", "In4c", "In4d"]]; allWires: Core.Wire _ SCTestUtil.UnionWire[pubWires, intWires]; i1a: CellInstance _ Inst[Inv, LIST["In1", "In1a"], "i1a"]; i1b: CellInstance _ Inst[Inv, LIST["In1", "In1b"], "i1b"]; i1c: CellInstance _ Inst[Inv, LIST["In1", "In1c"], "i1c"]; i1d: CellInstance _ Inst[Inv, LIST["In1", "In1d"], "i1d"]; i2a: CellInstance _ Inst[Inv, LIST["In2", "In2a"], "i2a"]; i2b: CellInstance _ Inst[Inv, LIST["In2", "In2b"], "i2b"]; i2c: CellInstance _ Inst[Inv, LIST["In2", "In2c"], "i2c"]; i2d: CellInstance _ Inst[Inv, LIST["In2", "In2d"], "i2d"]; i3a: CellInstance _ Inst[Inv, LIST["In3", "In3a"], "i3a"]; i3b: CellInstance _ Inst[Inv, LIST["In3", "In3b"], "i3b"]; i3c: CellInstance _ Inst[Inv, LIST["In3", "In3c"], "i3c"]; i3d: CellInstance _ Inst[Inv, LIST["In3", "In3d"], "i3d"]; i4a: CellInstance _ Inst[Inv, LIST["In4", "In4a"], "i4a"]; i4b: CellInstance _ Inst[Inv, LIST["In4", "In4b"], "i4b"]; ShortInst: CellInstance _ Inst[Short, LIST["In4", "OutDummy"], "ShortInst"]; InvInst: CellInstance _ Inst[Inv, LIST["In4", "OutInv"], "InvInst"]; NAnd2Inst: CellInstance _ Inst[NAnd2, LIST["In1a", "In2a", "OutNAnd2"], "NAnd2Inst"]; NOr2Inst: CellInstance _ Inst[NOr2, LIST["In1b", "In2b", "OutNOr2"], "NOr2Inst"]; Or2Inst: CellInstance _ Inst[Or2, LIST["In1c", "In2c", "OutOr2"], "Or2Inst"]; And2Inst: CellInstance _ Inst[And2, LIST["In1d", "In2d", "OutAnd2"], "And2Inst"]; NAnd3Inst: CellInstance _ Inst[NAnd3, LIST["In1a", "In2a", "In3a", "OutNAnd3"], "NAnd3Inst"]; NOr3Inst: CellInstance _ Inst[NOr3, LIST["In1b", "In2b", "In3b", "OutNOr3"], "NOr3Inst"]; Or3Inst: CellInstance _ Inst[Or3, LIST["In1c", "In2c", "In3c", "OutOr3"], "Or3Inst"]; And3Inst: CellInstance _ Inst[And3, LIST["In1d", "In2d", "In3d", "OutAnd3"], "And3Inst"]; NAnd4Inst: CellInstance _ Inst[NAnd4, LIST["In1a", "In2a", "In3a", "In4a", "OutNAnd4"], "NAnd4Inst"]; NOr4Inst: CellInstance _ Inst[NOr4, LIST["In1b", "In2b", "In3b", "In4a", "OutNOr4"], "NOr4Inst"]; Or4Inst: CellInstance _ Inst[Or4, LIST["In1c", "In2c", "In3c", "In4b", "OutOr4"], "Or4Inst"]; And4Inst: CellInstance _ Inst[NOr4, LIST["In1d", "In2d", "In3d", "In4b", "OutAnd4"], "And4Inst"]; XorInst: CellInstance _ Inst[Xor, LIST["In3a", "In4a", "OutXor"], "XorInst"]; XnorInst: CellInstance _ Inst[Xnor, LIST["In3b", "In4b", "OutXnor"], "XnorInst"]; Latch1Inst: CellInstance _ Inst[Latch1, LIST["In1a", "In2a", "OutL1Q", "OutL1NQ"], "Latch1Inst"]; Latch2Inst: CellInstance _ Inst[Latch2, LIST["In1b", "In2b", "OutL2Q", "OutL2NQ"], "Latch2Inst"]; Latch3Inst: CellInstance _ Inst[Latch3, LIST["In1c", "In2c", "In3d", "OutL3Q", "OutL3NQ"], "Latch3Inst"]; Latch4Inst: CellInstance _ Inst[Latch4, LIST["In1d", "In2d", "In3d", "OutL4Q", "OutL4NQ"], "Latch4Inst"]; SCTest: CellType _ SCTestUtil.CreateRecordCell["SCTest", pubWires, allWires, LIST[ i1a, i1b, i1c, i1d, i2a, i2b, i2c, i2d, i3a, i3b, i3c, i3d, i4a, i4b, ShortInst, InvInst, NAnd2Inst, NOr2Inst, And2Inst, Or2Inst, NAnd3Inst, NOr3Inst, And3Inst, Or3Inst, NAnd4Inst, NOr4Inst, And4Inst, Or4Inst, XorInst, XnorInst, Latch1Inst, Latch2Inst, Latch3Inst, Latch4Inst ] ]; IF debug THEN { out: IO.STREAM _ ViewerIO.CreateViewerStreams[ name: "Core: SCTest", viewer: NIL, editedStream: FALSE].out; CoreOps.PrintCellType[SCTest, out] }; RETURN [SCTest]; END; END.  CJInterior.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. 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