<> <> <> <> <<>> DIRECTORY CD, CDIO, CDOps, CoreClasses, CoreCreate, CoreProperties, PWCore, Rope, SC; SCMacros: CEDAR PROGRAM IMPORTS CDIO, CDOps, PWCore, SC = BEGIN OPEN CoreCreate; ROPE: TYPE = Rope.ROPE; SCLayoutAtom: ATOM _ PWCore.RegisterLayoutAtom[$SC, StandardCellLayout, NIL]; <<-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.>> StandardCellLayout: PWCore.LayoutProc = { flatCT: CellType _ FlattenCT[cellType]; cdDesign: CD.Design _ CDOps.CreateDesign[libDesign.technology]; obj _ SC.CreateLayout[ technologyKey: cdDesign.technology.key, horizLayer: "metal", vertLayer: "metal2", rowDirection: horizontal, numRows: 1, cellType: flatCT, cdDesign: cdDesign, libDesign: libDesign, name: "SCTestSmall"] }; <<-- Flatten until the cellType has a $Layout property>> <> <> <> <<};>> <> <<};>> <<>> FlattenCT: PROC [cellType: CellType] RETURNS [flatCT: CellType] ~ { flatCT _ cellType; }; libName: ROPE _"SCLibCMOSB.dale"; -- we should get rid of this design libDesign: CD.Design _ CDIO.ReadDesign[libName]; -- schematics representation of standard cells END.