<> <> <> <> <<>> <<-- This module provides basic blocks for logic description and simulation of ICs. Every procedure corresponds to an icon in the library "Logic.dale" i.e. extracting such an icon using Sisyph will call the corresponding procedure. The difference with a library like SSI is that there is no electrical notion attached to the cells, only logic behavior.>> <<-- There are two types of cells in this library: the simple ones and the composite ones. The simple ones (inverter, nor4, ...) are similar to the cells in SSI and have usually a corresponding standard cell in most decent libraries. The composite ones (i.e. adder) have a Core structure using cells of the first type as leaves. Both have a behavioral procedure for simulating using Rosemary.>> <<>> DIRECTORY CoreCreate, Ports, Sisyph; Logic: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <<>> <<-- Very basic standard cells>> Vdd: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd">> Gnd: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd">> Inv: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> InvBuffer: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> <<>> And2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> And3: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "X">> And4: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "I-D", "X">> Nand2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Nand3: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "X">> Nand4: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "I-D", "X">> Or2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Or3: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "X">> Or4: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "I-D", "X">> Nor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Nor3: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "X">> Nor4: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "I-C", "I-D", "X">> Xor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Xnor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> <<>> invMux2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "selA", "nOut">> MSFlipFlop: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK", "nR", "nP">> Latch1: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "E", "nR", "nP">> <<>> <<-- Composite (macros)>> Register: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "nE", "nCl">> Latch : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "E", "cl">> TstBuffer : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "E">> <<>> Adder: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut">> ALU: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut", Seq["F", 8]>> Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Output", b]>> <

> Comparator: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["A", i], Seq["B", i], "AEqB">> <<>> Mux2: PROC [b: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["Output", b]>> Mux3: PROC [b: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", 2], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["Output", b]>> Mux4: PROC [b: NAT, i: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", i], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b]>> <<>> Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["nSelect", s], "nEnable">> < s _ 2**a>> <<>> Counter: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CountA", "CountB", "Load", "UpNDown", Seq["Input", b], Seq["Output", b]>> <<>> ShiftRegister: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "ShiftA", "ShiftB", "Load", "LeftNRight", "LeftInput", "RightInput", Seq["Input", b], Seq["Output", b]>> <<>> OnePortRam: PROC [b: NAT, a: NAT, w: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", Seq["Address", a], Seq["Input", b], Seq["Output", b]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> TwoPortRam: PROC [b: NAT, a: NAT, w: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", Seq["Address", a], Seq["Input", b], Seq["Output", b]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> ThreePortRam: PROC [b: NAT, a: NAT, w: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", Seq["Address", a], Seq["Input", b], Seq["Output", b]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> ROM: PROC [b: NAT, a: NAT, w: NAT _ 0, rp: NAT _ 1, wp: NAT _ 1] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Load", wp], Seq["WriteAddress", wp, Seq[size: a]], Seq["ReadAddress", rp, Seq[size: a]], Seq["Input", wp, Seq[size: b]], Seq["Output", rp, Seq[size: b]]>> <> < w _ 2**a>> < 2**a => ERROR>> PLA: PROC [b: NAT, a: NAT, w: NAT _ 0, rp: NAT _ 1, wp: NAT _ 1] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Load", wp], Seq["WriteAddress", wp, Seq[size: a]], Seq["ReadAddress", rp, Seq[size: a]], Seq["Input", wp, Seq[size: b]], Seq["Output", rp, Seq[size: b]]>> <> < w _ 2**a>> < 2**a => ERROR>> <<>> <<>> -- **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** <<>> <<-- These belong in Sch, but Sch must be redone, so in the mean time...>> SetObjectPort: PROC [cx: Sisyph.Context, initType: Ports.PortType _ b, initDrive: Ports.Drive _ none]; SetObjectTesterDrive: PROC [cx: Sisyph.Context, initDrive: Ports.Drive _ none]; ClockGen: PROC [up, dn, firstUp: NAT] RETURNS [ct: CellType]; <<"Time", "Clock">> END.