SXCMosTransistorsImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Last edited by: gbb March 26, 1986 2:47:23 pm PST
Bowers, October 9, 1985 4:03:32 pm PDT
Last edited by: Christian Jacobi, November 7, 1986 4:53:01 pm PST
DIRECTORY
CD,
CDAtomicObjects USING [AtomicObsSpecific, DrawList],
CDBasics USING [empty, highposition, minposition, NonEmpty],
CDProperties USING [GetInstanceProp],
CDSimpleRules USING [MinDist],
CMos USING [lambda, ndif, nwell, pdif, pol, pwell, wndif, wpdif],
CMosCMTransistors USING [TransistorPtr],
IO USING [char, int, Put, PutF, PutRope, rope],
PropertyLists USING [PutProp],
Rope USING [Cat, ROPE],
SX USING [AddBox, AddRect, AdjustNode, AttachedNode, Circuit, CircuitNode, Constraint, ConversionProc, CreateLinkage, IllegalConstruct, LinkageAttach, NodeLinkage, SpinifexLayerIndex],
SXAtoms USING [crystalAttr],
SXCMos USING [ndCh, ndCnstr, ndifSpinifex, pChE, pdCh, pdCnstr, pdifSpinifex, pExnD, pExpD, polCnstr, polSpinifex],
SXCMosBasicRules USING [difToPolExtSep, difToPolSep],
SXOutput USING [LinkagePrintProc],
SXOutputPrivate USING [GetANaming, NameTransType, Naming, PrintNaming, PrintRoseInstantiationTransformation],
SXTechnology USING [ESWGrow, NESGrow, PerDrawRectProc, ProcessMosTransistor, WNEGrow, WNGrow],
TerminalIO USING [PutRope];
SXCMosTransistorsImpl: CEDAR PROGRAM
IMPORTS CD, CDBasics, CDProperties, CDSimpleRules, CMos, IO, PropertyLists, Rope, SX, SXAtoms, SXCMos, SXOutputPrivate, SXTechnology, TerminalIO
EXPORTS SXCMos =
BEGIN
OPEN SXCMos;
l: CD.Number ~ CMos.lambda;
Nodes: TYPE = LIST OF REF SX.CircuitNode;
MapMaterial: SXTechnology.PerDrawRectProc -- [r: CD.Rect, l: CD.Layer, data: REF ANY] RETURNS [TransistorMaterial] -- ~ {
cir: REF SX.Circuit ~ NARROW [data, REF SX.Circuit];
SELECT l FROM
CMos.ndif, CMos.pdif => RETURN [diffusion];
CMos.pol => RETURN [polysilicon];
CMos.nwell => {
wellNode: REF SX.CircuitNode ← cir.AddRect [lev~ CMos.nwell, dim~ r];
wellNode.properties ← PropertyLists.PutProp [wellNode.properties, wellNode, wellNode];
RETURN [nothing];
};
ENDCASE => RETURN [nothing];
}; -- MapMaterial
ConvTransistor: PUBLIC SX.ConversionProc =
New transistor conversion procedure for ChipNDale 2.1
PROCEDURE [inst: CD.Instance, pos: CD.Position, orient: CD.Orientation, cir: REF Circuit]
BEGIN
transistor: REF SX.NodeLinkage;
gateNode, sourceNode, drainNode, wellNode: REF SX.CircuitNode;
tClass: ATOM = inst.ob.class.objectType;
isNType: BOOL = (inst.ob.layer = CMos.ndif);
isNWell: BOOL;
difSXLayer: SX.SpinifexLayerIndex;
difChannel, exclPol: REF SX.Constraint;
sep: CD.Number = SXCMosBasicRules.difToPolSep;
extSep: CD.Number = SXCMosBasicRules.difToPolExtSep;
rect, wellRect: CD.Rect;
polList, difList, chList, difListSouth: LIST OF CD.Rect ← NIL;
length, width, extL, extW: CD.Number;
gateA, gateP, sourceA, sourceP, drainA, drainP: INT; -- ignore perimeter leading into channel
errorRect: CD.Rect = CD.InterestRect [inst.ob];
Determine diffusion layer and channel constraint
IF isNType THEN
{difSXLayer ← ndifSpinifex; difChannel ← ndCnstr[ndCh]; exclPol ← polCnstr[pExnD]}
ELSE
{difSXLayer ← pdifSpinifex; difChannel ← pdCnstr[pdCh]; exclPol ← polCnstr[pExpD]};
Get the geometry. Streching information has already been procesed by ChipNDale.
wellRect ← CDBasics.empty;
IF ISTYPE [inst.ob.specific, CDAtomicObjects.AtomicObsSpecific] THEN
FOR geom: CDAtomicObjects.DrawList ← NARROW [inst.ob.specific, CDAtomicObjects.AtomicObsSpecific].rList, geom.rest WHILE geom # NIL DO
SELECT geom.first.layer FROM
CMos.pol => polList ← CONS [geom.first.r, polList];
CMos.ndif, CMos.pdif => difList ← CONS [geom.first.r, difList];
CMos.nwell, CMos.pwell => {wellRect ← geom.first.r; isNWell ← (geom.first.layer = CMos.nwell)};
ENDCASE => ERROR SX.IllegalConstruct [geom.first.r, "Unknown transistor geometry"];
ENDLOOP
ELSE -- an old Chipmonk transistor
BEGIN
dim: CMosCMTransistors.TransistorPtr;
IF NOT ISTYPE [inst.ob.specific, CMosCMTransistors.TransistorPtr] THEN
ERROR SX.IllegalConstruct [errorRect, "Unknown transistor geometry"];
dim ← NARROW [inst.ob.specific, CMosCMTransistors.TransistorPtr];
The following data is supposed to be correct by convention.
length ← dim.length; width ← dim.width;
extL ← dim.lExt; extW ← dim.wExt;
gateA ← (width + 2*extW) * length; gateP ← (width + 2*extW + length) * 2;
sourceA ← drainA ← extL * width; sourceP ← drainP ← 2 * extL + width
END;
Process the geometry according to the transistor class. The ChipNDale transistors are fully supported for p substrate. The Chipmonk angle transistors are still supported using the corner stitching method. The old Chipmonk transistors $CMosTransistor and $CMosPTypeTransistor are no longer supported.
SELECT tClass FROM
$CTrans, $CWellTrans => -- straight transistors
BEGIN
difRect, polRect, chRect, difExtRectNorth, difExtRectSouth: CD.Rect;
difRect ← difList.first; polRect ← polList.first;
chRect ← [difRect.x1, polRect.y1, difRect.x2, polRect.y2];
difExtRectNorth ← difExtRectSouth ← difRect;
difExtRectNorth.y1 ← polRect.y2; difExtRectSouth. y2 ← polRect.y1;
length ← polRect.y2 - polRect.y1; width ← difRect.x2 - difRect.x1;
extL ← polRect.y1 - difRect.y1; extW ← difRect.x1 - polRect.x1;
gateA ← (width + 2*extW) * length; gateP ← (width + 2*extW + length) * 2;
sourceA ← drainA ← extL * width; sourceP ← drainP ← 2 * extL + width;
Process poly layer
gateNode ← SX.AddRect [cir: cir, lev: CMos.pol, dim: polRect, trans: trans];
IF extL > sep THEN -- Add rectangles for poly exclusion
BEGIN
rect ← difExtRectNorth; rect.y1 ← rect.y1 + sep;
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.WNEGrow [extSep], exclPol];
rect ← difExtRectSouth; rect.y2 ← rect.y2 - sep;
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.ESWGrow [extSep], exclPol];
END;
Process channel lead-in
rect ← difExtRectNorth; rect.y2 ← rect.y1+sep;
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]];
rect ← difExtRectSouth; rect.y1 ← rect.y2-sep;
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]];
Fill channel gap. NOTE: The DRC of channels is affected by the change made to CMosSpinifexInitImpl on April 2, 1985.
[] ← SX.AddBox [cir: cir, spinifexLayer: difSXLayer,
dim: chRect, trans: trans,
interestBloat: [dx1: (CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2), dy1: 0, dx2: (CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2), dy2: 0],
value: difChannel];
Add rectangles for diff width spacing and connection
sourceNode ← SX.AddBox[cir: cir, spinifexLayer: difSXLayer,
dim: difExtRectNorth, trans: trans,
interestBloat: SXTechnology.WNEGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)]];
drainNode ← SX.AddBox[cir: cir, spinifexLayer: difSXLayer,
dim: difExtRectSouth, trans: trans,
interestBloat: SXTechnology.ESWGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)]];
Process well.
IF tClass = $CWellTrans THEN
BEGIN
l: CD.Layer = IF isNWell THEN CMos.nwell ELSE CMos.pwell;
IF NOT CDBasics.NonEmpty[wellRect] THEN ERROR SX.IllegalConstruct [errorRect, "Well transistor must have a well"];
wellNode ← SX.AddRect [cir: cir, lev: l, dim: wellRect, trans: trans];
wellNode.properties ← PropertyLists.PutProp [propList: wellNode.properties, prop: wellNode, val: wellNode];
END;
END; -- case $CTrans
$CLTrans, $CLWellTrans => -- angle transistors
BEGIN
diffNE: CD.Position ← CDBasics.minposition;
diffSW, polSW: CD.Position ← CDBasics.highposition;
polHor, polVert: CD.Rect;
IF ((polList.first.y2-polList.first.y1) < (polList.rest.first.y2-polList.rest.first.y1)) THEN
{polHor ← polList.first; polVert ← polList.rest.first}
ELSE {polHor ← polList.rest.first; polVert ← polList.first};
FOR diff: LIST OF CD.Rect ← difList, diff.rest WHILE diff # NIL DO
IF (diff.first.x1 <= diffSW.x) AND (diff.first.y1 <= diffSW.y) THEN
diffSW ← [diff.first.x1, diff.first.y1];
IF (diff.first.x2 >= diffNE.x) AND (diff.first.y2 >= diffNE.y) THEN
diffNE ← [diff.first.x2, diff.first.y2];
ENDLOOP;
polSW ← [polHor.x1, polHor.y1];
extW ← diffSW.x - polSW.x;
extL ← polSW.y - diffSW.y;
length ← polHor.y2 - polHor.y1;
width ← ((polHor.x2 - polHor.x1) - extW) + ((polVert.y2 - polVert.y1) - extW) - (length*3/2);
gateA ← ((width+length/2) + 2*extW) * length;
gateP ← ((polHor.x2 - polHor.x1) + (polVert.y2 - polVert.y1)) * 2;
sourceA ← ((diffNE.x - diffSW.x) + (diffNE.y - diffSW.y - extL)) * extL;
sourceP ← 2 * extL + (diffNE.x - diffSW.x) + (diffNE.y - diffSW.y);
drainP ← diffNE.x + diffNE.y - diffSW.x - diffSW.y - 2 * (extL + length);
drainA ← drainP * extL;
Process poly layer
gateNode ← SX.AddRect [cir: cir, lev: CMos.pol, dim: polHor, trans: trans];
[] ← SX.AddRect [cir: cir, lev: CMos.pol, dim: polVert, trans: trans, value: gateNode];
IF extL > sep THEN -- Add rectangles for poly exclusion
BEGIN
d: CD.Number ← extL + length + sep;
rect ← [x1: diffSW.x, y1: diffSW.y+d, x2: diffNE.x-d, y2: diffSW.y+length+2*extL];
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.WNGrow [extSep], exclPol]; -- North
rect ← [x1: diffNE.x-length-2*extL, y1: diffSW.y+d, x2: diffNE.x-d, y2: diffNE.y];
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.WNGrow [extSep], exclPol]; -- West
d ← extL - sep;
rect ← [x1: diffSW.x, y1: diffSW.y, x2: diffNE.x, y2: diffSW.y+d];
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.ESWGrow [extSep], exclPol]; -- South
rect ← [x1: diffNE.x-d, y1: diffSW.y, x2: diffNE.x, y2: diffNE.y];
[] ← SX.AddBox [cir, polSpinifex, rect, trans, SXTechnology.NESGrow [extSep], exclPol] -- East
END; -- poly excl
Process channel lead-in
BEGIN
d: CD.Number ← extL + length + sep;
rect ← [x1: diffSW.x, y1: diffSW.y+extL+length, x2: diffNE.x-extL-length, y2: diffSW.y+d];
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]]; -- North
rect ← [x1: diffNE.x-d, y1: diffSW.y+extL+length, x2: diffNE.x-extL-length, y2: diffNE.y];
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]]; -- West
d ← extL - sep;
rect ← [x1: diffSW.x, y1: diffSW.y+d, x2: diffNE.x-d, y2: diffSW.y+extL];
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]]; -- South
rect ← [x1: diffNE.x-extL, y1: diffSW.y+d, x2: diffNE.x-d, y2: diffNE.y];
[] ← SX.AddBox [cir: cir, spinifexLayer: polSpinifex, dim: rect, trans: trans, value: polCnstr[pChE]] -- East
END; -- ch lead-in
Fill channel gap. NOTE: The DRC of channels is affected by the change made to CMosSpinifexInitImpl on April 2, 1985.
rect ← polHor; rect.x1 ← rect.x1 + extW;
[] ← SX.AddBox [cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: [dx1: (CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2), dy1: 0, dx2: 0, dy2: 0],
value: difChannel];
rect ← polVert; rect.y2 ← rect.y2 - extW;
[] ← SX.AddBox [cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: [dx1: 0, dy1: 0, dx2: 0, dy2: (CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)],
value: difChannel];
Add rectangles for diff width spacing and connection
rect ← [x1: diffSW.x, y1: diffSW.y+extL+length, x2: diffNE.x-extL-length, y2: diffSW.y+2*extL+length];
sourceNode ← SX.AddBox [cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: SXTechnology.WNGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)]];
IF difList.rest # NIL THEN -- supposed source is concave
BEGIN
rect ← [x1: diffNE.x-length-2*extL, y1: rect.y1, x2: rect.x2, y2: diffNE.y];
[] ← SX.AddBox [cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: SXTechnology.WNGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)],
value: sourceNode]
END;
rect ← [x1: diffSW.x, y1: diffSW.y, x2: diffNE.x, y2: diffSW.x+extL];
drainNode ← SX.AddBox[cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: SXTechnology.ESWGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)]];
rect ← [x1: diffNE.x-extL, y1: rect.y2, x2: diffNE.x, y2: diffNE.y];
[] ← SX.AddBox[cir: cir, spinifexLayer: difSXLayer,
dim: rect, trans: trans,
interestBloat: SXTechnology.NESGrow[(CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2)],
value: drainNode];
Process well.
IF tClass = $CWellTrans THEN
BEGIN
l: CD.Layer = IF isNWell THEN CMos.nwell ELSE CMos.pwell;
IF NOT CDBasics.NonEmpty[wellRect] THEN ERROR SX.IllegalConstruct [errorRect, "Well transistor must have a well"];
wellNode ← SX.AddRect [cir: cir, lev: l, dim: wellRect, trans: trans];
wellNode.properties ← PropertyLists.PutProp [propList: wellNode.properties, prop: wellNode, val: wellNode];
END;
END; -- case $CTrans
$CMosTransistor, $CMosPTypeTransistor => ERROR SX.IllegalConstruct [errorRect, "This kind of Chipmonk transistors is no longer supported"];
$CMosATransistor, $CMosPTypeATransistor =>  -- Chipmonk angle transistors
BEGIN
sourceDrainList: Nodes;
sourceDrainCount: INTEGER;
[gateNode, sourceDrainList, sourceDrainCount] ← SXTechnology.ProcessMosTransistor[inst, trans, cir, difSXLayer, polSpinifex, difChannel, polCnstr[pChE], (CDSimpleRules.MinDist[CMos.ndif, CMos.ndif]/2), SXCMosBasicRules.difToPolSep, MapMaterial, cir];
IF sourceDrainCount = 2 THEN {
sourceNode ← sourceDrainList.first;
drainNode ← sourceDrainList.rest.first;
}
ELSE {
TerminalIO.PutRope [Rope.Cat["Xstr with ", (
SELECT sourceDrainCount FROM
0 => "no",
1 => "only 1",
ENDCASE => "more than 2"),
" sources/drains not included in circuit description\n"
]];
RETURN
}
END; -- Chipmonk angle transistors
ENDCASE => ERROR SX.IllegalConstruct [errorRect, "Unknown transistor class"];
transistor ← SX.CreateLinkage [cir, inst, length, width];
Adjust area and perimeter values
SX.AdjustNode [node: gateNode, layer: polSpinifex, area: gateA, perim: gateP, mode: absolute];
SX.AdjustNode [sourceNode, difSXLayer, sourceA, sourceP, absolute];
SX.AdjustNode [drainNode, difSXLayer, drainA, drainP, absolute];
SX.LinkageAttach [link: transistor, attachType: $Gate, node: gateNode];
SX.LinkageAttach [link: transistor, attachType: $Source, node: sourceNode];
SX.LinkageAttach [link: transistor, attachType: $Drain, node: drainNode]
END; -- ConvTransistor
RoseTransistor: PUBLIC SXOutput.LinkagePrintProc -- [desWDir: ROPE, dfStream, cellStream: IO.STREAM, linkage: REF NodeLinkage, name: Rope.ROPE, PrintNode: NodePrintProc] -- ~ {
PrintAttachment: PROCEDURE [key: ATOM, portName: Rope.ROPE] ~ {
cellStream.Put [IO.rope[" (\""], IO.rope[portName], IO.rope["\" "]];
FOR attachments: LIST OF REF SX.AttachedNode ← linkage.nodes, attachments.rest WHILE attachments # NIL DO
IF attachments.first.attachmentType = key THEN {
PrintNode[cellStream, attachments.first.node];
cellStream.PutRope[")"];
RETURN
}
ENDLOOP;
cellStream.PutRope ["\"?\")"];
}; -- PrintAttachment
naming: SXOutputPrivate.Naming ← SXOutputPrivate.GetANaming [linkage.source];
cellStream.PutRope["(CI "];
SXOutputPrivate.PrintNaming[
cellStream,
naming,
Rope.Cat[" \"", SXOutputPrivate.NameTransType[
desWDir: desWDir,
obj: linkage.source.ob,
dfStream: dfStream,
type: SELECT linkage.source.ob.layer FROM
CMos.ndif, CMos.wndif => $n,
CMos.pdif, CMos.wpdif => $p,
ENDCASE => $funny,
mode: $E,
length: linkage.l,
width: linkage.w], "\""]
];
SXOutputPrivate.PrintRoseInstantiationTransformation[cellStream, linkage.source];
cellStream.PutRope [" (CIC"];
PrintAttachment [$Gate, "gate"];
PrintAttachment [$Source, "ch1"];
PrintAttachment [$Drain, "ch2"];
cellStream.PutRope ["))"]
}; -- RoseTransistor
ThymeTransistor: PUBLIC SXOutput.LinkagePrintProc -- [desWDir: ROPE, dfStream, cellStream: IO.STREAM, linkage: REF NodeLinkage, name: Rope.ROPE, PrintNode: NodePrintProc] -- ~ {
PrintAttachment: PROCEDURE [key: ATOM] ~ {
FOR attachments: LIST OF REF SX.AttachedNode ← linkage.nodes, attachments.rest WHILE attachments # NIL DO
IF attachments.first.attachmentType = key THEN {
PrintNode[cellStream, attachments.first.node];
RETURN
}
ENDLOOP;
cellStream.Put [IO.char['?]];
}; -- PrintAttachment
defaultW: INTEGER = 4*lambda;
defaultL: INTEGER = 2*l;
propertyValue: REF;
cellStream.Put [IO.rope[name], IO.rope[": "]];
cellStream.PutRope [SELECT linkage.source.ob.layer FROM
CMos.ndif, CMos.wndif => "ETran[",
CMos.pdif, CMos.wpdif => "CTran[",
ENDCASE => "FunnyTran["
];
PrintAttachment [$Gate];
cellStream.Put [IO.char[',]];
PrintAttachment [$Source];
cellStream.Put [IO.char[',]];
PrintAttachment [$Drain];
cellStream.Put [IO.char['|]];
cellStream.PutF[" W←N*%g", IO.int[linkage.w/l]];
IF linkage.l # defaultL THEN cellStream.PutF[", L←%g", IO.int[linkage.l/l]];
The following is a quick hack to allow John Ousterhout to test Crystal. In a later stage, SX.AttachedNode shall receive an additional field for this info. At the moment it is not clear yet, how the user interface should be like.
propertyValue ← CDProperties.GetInstanceProp [from: linkage.source, prop: SXAtoms.crystalAttr];
WITH propertyValue SELECT FROM
crystalHack: Rope.ROPE => IO.Put [stream: cellStream, v1: IO.rope["; "], v2: IO.rope[crystalHack]];
ENDCASE => IF propertyValue # NIL THEN TerminalIO.PutRope [" $Crystal property must be a rope./n"];
cellStream.PutRope ["];"]
}; -- ThymeTransistor
END.
Edited on March 7, 1985 1:44:59 am PST, by Shand
changes to: ConvTransistor Added Interest bloat to $DifChannel constraint to detect Dif to Channel spacing interactions.
Edited on March 7, 1985 4:30:02 pm PST, by Shand
Transistor Output changes: n*W multiplier for McCreight
Edited on March 12, 1985 1:42:54 pm PST, by Shand
changes to: ConvTransistor
Edited on March 16, 1985 5:50:52 pm PST, by Beretta
Introduced hack to handle burried contacts represented as atomic Chipndale object. In a possibly near future this hack shall be replaced by an analysis of the atomic Chipndale object.
Edited on March 19, 1985 12:41:05 pm PST, by Beretta
Thyme output change: substituted `n' coefficient for Ed McCreight by `N'
changes to: ThymeTransistor
Edited on May 1, 1985 4:15:10 pm PDT, by Beretta
Added a quick hack to the Thyme output to allow John Ousterhout to test Crystal.
changes to: ThymeTransistor: If a transistor has a property crystalAttr, then its rope value is placed in the parameter list, preceded by a semicolon.
Edited on May 6, 1985 11:26:55 am PDT, by Beretta
Converted to ChipNDale CD20
Edited on June 18, 1985 4:59:38 pm PDT, by Beretta
Changed transistor types from FooTrans to FooTran, as Thyme expects.
changes to: ThymeTransistor
Last edited by: gbb July 18, 1985 4:47:07 pm PDT
Converted to ChipNDale 2.1.
changes to: ConvTransistor: Adapted by Christian, ConvertContact: Completely rewritten.
Last edited by: gbb July 19, 1985 6:35:20 pm PDT
Reimplemented transistor conversion.
changes to: ConvTransistor
gbb August 9, 1985 2:19:39 pm PDT
Added MakeCoreTransistor.
gbb August 20, 1985 1:43:11 pm PDT
Core definition module was changed. CoreRecordCells became CoreRecord, RecordCell became RecordCellType, InstanceRec became CellInstanceRec, Instance became CellInstance, InstanceList became CellInstanceList
gbb November 24, 1985 4:19:54 pm PST
Removed MakeCoreTransistor.
changes to: DIRECTORY, SXCMosTransistorsImpl