DIRECTORYCore,CoreFlat,HashTable,IO,Rope,TiogaFileOps;SpiceOps: CEDAR DEFINITIONS = BEGINFlatWire: TYPE = CoreFlat.FlatWire;ConvData: TYPE = REF ConvDataRec;ConvDataRec: TYPE = RECORD[rootCell: Core.CellType,rootNode: TiogaFileOps.Ref,wTable: HashTable.Table,invTable: HashTable.Table,nextId: CARD _ 0,initList: Rope.ROPE,tranList: Rope.ROPE,printList: Rope.ROPE,optList: Rope.ROPE,temp: REAL _ 27.0,limpts: INT];gndName: Rope.ROPE;vddName: Rope.ROPE;pModel: Rope.ROPE;nModel: Rope.ROPE;diodeModel: Rope.ROPE;temp: REAL;pendingSimulations: HashTable.Table;simNumber: LONG CARDINAL;spiceModel,spiceOptions,spiceExtraLine: ATOM;WriteSpiceDeck: PROC [cellType: Core.CellType, outputFile: Rope.ROPE _ NIL];InitSpiceDeck: PROC [cellType: Core.CellType, outputFile: Rope.ROPE _ NIL] RETURNS [convData: ConvData];CloseSpiceDeck: PROC  [convData: ConvData, outputFile: Rope.ROPE];DisplaySpiceListing: PROC [listingFile: Rope.ROPE];Comment: PROC [convData: ConvData, comment: Rope.ROPE];Resistor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, tc1, tc2: REAL _ 0.0];Capacitor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL _ 0.0];Inductor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL _ 0.0];CoupledInductors: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, l1, l2: REAL, k: REAL];LosslessLine: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, z0: REAL, td: REAL];Vccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];Vcvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];Cccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];Ccvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];Diode: PROC [convData: ConvData, n1, n2: FlatWire, model: Rope.ROPE, area: REAL];VSource: PROC [convData: ConvData, n1, n2: FlatWire, dc: REAL _ 0.0];ISource: PROC [convData: ConvData, n1, n2: FlatWire, ma: REAL _ 0.0];PulseVS: PROC [convData: ConvData, n1, n2: FlatWire, v1, v2, td, tr, tf, pw, per: REAL _ 0.0];MOSFet: PROC [convData: ConvData, gate, drain, source, bulk: FlatWire, model: Rope.ROPE, l, w: REAL];END.   D  SpiceOps.mesaChristian LeCocq March 2, 1987 4:12:28 pm PSTTypesDefault names and valuesOptional specificationspoints to a Rope.ROPE which is used for the model field of the line corresponding to the cell.points to a Rope.ROPE which is concatenated with the .OPT line content.points to a Rope.ROPE which is inserted as a separate line in the file.Translation to and from Spice formatin SpiceInputGenImpl.mesa :two lower level ones to use in case one wants to generate a spice deck from custom data:in SpiceOutputViewImpl.mesa :Elements to Spice input line procsÊ÷  ˜ codešœ™K™-K™ —šÏk	˜	K˜Kšœ	˜	K˜
Kšœ˜Kšœ˜Kšœ˜K˜ —KšÑblnœœ˜#head™Kšœ
œ˜#šœ
œœ˜!šœœœ˜K˜Kšœ˜K˜K˜Kšœœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœœ˜Kšœ˜K˜———™Kšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœœ˜Kšœ$˜$Kšœœœ˜—™˜Kšœ^™^—˜KšœG™G—šœœ˜KšœG™G——™$Lšœ™KšÏnœœ,
œ˜LK™XKšŸœœ,
œœ˜hKšŸœœ-˜BLšœ™KšŸœœœ˜3—™"KšŸœœ*˜7KšŸœœ/œœ˜YKšŸ	œœ/œ
œ˜XKšŸœœ/œ
œ˜WKšŸœœ8œœ˜]KšŸœœ4œœ˜VKšŸœœ7œ˜GKšŸœœ7œ˜GKšŸœœ7œ˜GKšŸœœ7œ˜GKšŸœœ@œ˜QKšŸœœ,œ˜EKšŸœœ,œ˜EKšŸœœEœ˜^KšŸœœSœ˜e—Kšœ˜— …—    „  ¿  