DIRECTORY CD, Core, D2Basic, PWCore, Rope, Route, RTBasic, RTCoreUtil; SC: CEDAR DEFINITIONS = BEGIN RopeList: TYPE = LIST OF Rope.ROPE; Layer: TYPE = CD.Layer; Rect: TYPE = D2Basic.Rect; RefRect: TYPE = REF Rect; Pos: TYPE = D2Basic.Pos; Number: TYPE = D2Basic.Number; SideOrNone: TYPE = RTBasic.SideOrNone; Side: TYPE = RTBasic.Side; DirectionOrNone: TYPE = RTBasic.DirectionOrNone; Direction: TYPE = RTBasic.Direction; Properties: TYPE = Core.Properties; Error: ERROR [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; Signal: SIGNAL [signalType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; ErrorType: TYPE = {programmingError, callingError, noResource, other}; DesignRules: TYPE = REF DesignRulesRec; DesignRulesRec: TYPE = RECORD[ horizLayer, vertLayer: Rope.ROPE, rowRules, sideRules: Route.DesignRules, technology: PRIVATE REF ANY _ NIL, properties: Properties _ NIL]; CreateDesignRules: PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: Direction, properties: Properties _ NIL] RETURNS [designRules: DesignRules]; Handle: TYPE = REF HandleRec; HandleRec: TYPE = RECORD [ name: Rope.ROPE _ NIL, coreCellType: Core.CellType _ NIL, rules: DesignRules _ NIL, properties: Properties _ NIL, parms: PRIVATE REF ANY _ NIL, structureData: PRIVATE REF ANY _ NIL, layoutData: PRIVATE REF ANY _ NIL]; Result: TYPE = REF ResultRec; ResultRec: TYPE = RECORD[ handle: Handle, object: CD.Object, rect: Rect _ [0, 0, 0, 0], polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: NAT _ 0, numIncompletes: NAT _ 0, incompleteNets: RopeList _ NIL]; CreateHandle: PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE _ NIL, designRules: DesignRules, name: Rope.ROPE _ NIL, properties: Properties _ NIL] RETURNS [handle: Handle]; numRows: ATOM; sideProp, bottomSideValue, rightSideValue, topSideValue, leftSideValue, noSideValue: ATOM; rowProp: ATOM; positionProp: ATOM; leftPowerProp, rightPowerProp: ATOM; investmentProp, veryLongValue, longValue, mediumValue, shortValue, veryShortValue: ATOM; t0SA, alphaSA, eqVarLimitSA, fzVarLimitSA, eqTabSizeSA, fzTabSizeSA: ATOM; -- Used to specify DIRECTLY the investment to make in placement. bottomMaxExits, rightMaxExits, topMaxExits, leftMaxExits: ATOM; bottomExitSpacing, rightExitSpacing, topExitSpacing, leftExitSpacing: ATOM; interestingProperties: RTCoreUtil.PropertyKeys; InitialPlace: PROC [handle: Handle, numRows: NAT _ 0]; PosImprove: PROC [handle: Handle, maxCycles: INT _ 5]; OrientImprove: PROC [handle: Handle, maxCycles: INT _ 5]; HowLongToWork: TYPE = {veryLong, long, medium, short, veryShort, noInvestmentProp}; SAParms: TYPE = RECORD [ t0: REAL _ 100000.0, alpha: REAL _ 0.98, eqVarLimit: REAL _ 0.10, fzVarLimit: REAL _ 0.04, eqTabSize, fzTabSize: INT _ 200]; SAInitialResult: TYPE = RECORD [ minScore, maxScore, minDelta, maxDelta, avgDelta: REAL _ 0.0, numTotal, numDecrease, numIncrease, numNeutral: INT _ 0]; SAInitialPlace: PROC [handle: Handle, seed: INT _ 0] RETURNS [initialResult: SAInitialResult]; SAGetParms: PROC [handle: Handle, initialResult: SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SAParms]; SAPlaceImprove: PROC [handle: Handle, saParms: SAParms, seed: INT _ 0]; GlobalRoute: PROC [handle: Handle]; DetailRoute: PROC [handle: Handle] RETURNS [result: Result]; StandardCellLayout: PWCore.LayoutProc; StandardCellDecorate: PWCore.DecorateProc; StandardCellAttibutes: PUBLIC PWCore.AttributesProc; -- [cellType: Core.CellType] Destroy: PROC [handle: Handle]; CreateLayout: PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: Direction, numRows: NAT, cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE _ NIL, name: Rope.ROPE _ NIL, properties: Properties _ NIL] RETURNS [object: CD.Object]; END. ðSC.mesa Copyright c 1985, 1986 by Xerox Corporation. All rights reserved. Last Edited by: Preas, November 7, 1985 10:11:48 am PST Theory This interface defines the basic data structures and procedures to define a standard cell object from a Core description. Common Types Errors Design Rules Define the standard cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2". Standard Cell Handles and Results Create a StdCellHandle. The StdCellHandle definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition. Properties Used to specify the number of rows for a standard cell assembly. Should be a property on Core cellType being laid out Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire Used to specify the row on which a logic cell is to be placed. rowProp and and integer row number should be a property/value on a locig cell insatance Used to specify the position of a logic within a row or of an public pin on a side. May be used on public wire or a logic cell instance. Used to specify the side on which power busses are to be placed. May be used on 0, 1 or 2 public wires. Used to specify indirectly the investment to make in placement. Used to specify the maximum number or exits on a side. Used to specify the HINT for publics spacing on a side. Used to specify all the properties that aer interesting to SC Standard Cell Optimization and Construction The following operations are available for a standard cell design. Determine an initial placement for the instances. Improve the positions of instances whithin rows. Improve the orientation of instances. Initialize for simulated annealing improvement. determine parameters for simulated placement. Improve the placement for the instances by simulated annealing. Determine strategic paths for the wiring that must cross cell rows. Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object. 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