SCTestUtilImpl:
CEDAR
PROGRAM
IMPORTS CDCells, CDIO, CoreClasses, CoreCreate, CoreOps, PWCore, SC, TerminalIO
EXPORTS SCTestUtil =
BEGIN
CreateInstance:
PUBLIC
PROC [actual:
SC.RopeList, type: Core.CellType, name: Rope.
ROPE, internalWires: Core.Wire, props: Core.Properties ←
NIL]
RETURNS [instance: CoreClasses.CellInstance] = {
create a cell instance rec
actualWire: Core.Wire ← BindWire[actual, internalWires];
instance ← CoreClasses.CreateInstance[actualWire, type, name, props]};
CreateRecordCell:
PUBLIC
PROC [name: Rope.
ROPE, publicWires: Core.Wire, internalWires: Core.Wire ←
NIL, instances: CoreClasses.CellInstances ←
NIL, props: Core.Properties ←
NIL, libDesign:
CD.Design]
RETURNS [cellType: Core.CellType] = {
create a cell instance rec
cellType ← CoreClasses.CreateRecordCell[publicWires, internalWires, instances, name, props];
IF libDesign # NIL THEN PWCore.SetGet[cellType, libDesign]};
CreateWire:
PUBLIC
PROC [ropeList:
SC.RopeList]
RETURNS [wire: Core.Wire] ~ {
lowr: LIST OF CoreCreate.WR ← ConvertToWR[ropeList];
wire ← CoreCreate.WireList[lowr]};
AppendInstList:
PUBLIC
PROC [l1, l2: CoreClasses.CellInstances]
RETURNS[val: CoreClasses.CellInstances] = {
z: CoreClasses.CellInstances ← NIL;
val ← l2;
IF l1 = NIL THEN RETURN[val];
val ← CONS[l1.first, val];
z ← val;
UNTIL (l1 ← l1.rest) =
NIL
DO
z.rest ← CONS[l1.first, z.rest];
z ← z.rest;
ENDLOOP;
RETURN[val];
};
AppendRopeList:
PUBLIC
PROC [l1, l2:
SC.RopeList]
RETURNS[val: SC.RopeList] = {
z: SC.RopeList ← NIL;
val ← l2;
IF l1 = NIL THEN RETURN[val];
val ← CONS[l1.first, val];
z ← val;
UNTIL (l1 ← l1.rest) =
NIL
DO
z.rest ← CONS[l1.first, z.rest];
z ← z.rest;
ENDLOOP;
RETURN[val];
};
WriteLayout:
PUBLIC
PROC [result:
SC.Result, design:
CD.Design] =
Write a standard cell object to a CND design
BEGIN
[] ← CDCells.IncludeOb[design: design,
cell: NIL, ob: result.object, position: [0, 0], orientation: CD.original,
cellCSystem: interrestCoords, obCSystem: interrestCoords, mode: dontPropagate];
IF ~
CDIO.WriteDesign[design, result.handle.name]
THEN
TerminalIO.WriteRope["Error: design not written\n"];
END;
DoLayout:
PUBLIC
PROC [cellType: Core.CellType, flattenCellType: CoreFlat.FlattenCellTypeProc, libName: Rope.
ROPE, hMaterial, vMaterial: Rope.
ROPE]
RETURNS [result:
SC.Result ←
NIL] =
Create a standard cell object
BEGIN
libDesign: CD.Design ← CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];
rules: SC.DesignRules ← SC.CreateDesignRules[libDesign.technology.key, hMaterial, vMaterial, horizontal];
handle: SC.Handle ← SC.CreateHandle[cellType, flattenCellType, libName, rules, "SCTest"];
SC.InitialPlace[handle, 0];
SC.GlobalRoute[handle];
SC.PlaceImprove[handle];
result ← SC.DetailRoute[handle];
BindWire:
PROC [actual:
SC.RopeList, internalWires: Core.Wire]
RETURNS [actualWire: Core.Wire] = {
do wire binding by name
reverseWireList: LIST OF CoreCreate.WR ← NIL;
newWireList: LIST OF CoreCreate.WR ← NIL;
FOR rl:
SC.RopeList ← actual, rl.rest
UNTIL rl=
NIL
DO
r: Rope.ROPE ← rl.first;
index: INT ← CoreOps.GetWireIndex[internalWires, r];
IF index < 0 THEN SC.Error[callingError, NIL];
reverseWireList ← CONS[internalWires[index], reverseWireList];
ENDLOOP;
FOR rl:
LIST
OF CoreCreate.
WR ← reverseWireList, rl.rest
UNTIL rl=
NIL
DO
newWireList ← CONS[rl.first, newWireList];
ENDLOOP;
actualWire ← CoreCreate.WireList[newWireList];
};
UnionWire:
PUBLIC
PROC [wire1, wire2: Core.Wire, name: Rope.
ROPE ←
NIL, props: Core.Properties ←
NIL]
RETURNS [union: Core.Wire] ~ {
Creates a new structured wire of size wire1.size+wire2.size, with corresponding name and properties
RETURN [CoreOps.UnionWire[wire1, wire2]]};
ConvertToWR:
PROC [list:
SC.RopeList]
RETURNS[wrl:
LIST
OF CoreCreate.
WR ←
NIL] = {
reverseWireList: LIST OF CoreCreate.WR ← NIL;
UNTIL list =
NIL
DO
reverseWireList ← CONS[list.first, reverseWireList];
list ← list.rest;
ENDLOOP;
UNTIL reverseWireList =
NIL
DO
wrl ← CONS[reverseWireList.first, wrl];
reverseWireList ← reverseWireList.rest;
ENDLOOP;
RETURN[wrl];
}; -- of ConvertToWR
END.