Create a Core design

BEGIN

scCutSet: ATOM ← $SCPlacableElement;   -- leaf of the SC layout system

coreLibrary: CoreDirectory.Library ← CoreDirectory.CreateLibrary[];

libDesign: CD.Design ← CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];

feedthruWires: Core.Wire ← RTTestUtil.CreateWire[LIST["InOut", "Vdd", "Gnd"]];

feedthru: Core.CellType ← RTTestUtil.CreateRecordCell["feedthru", feedthruWires, feedthruWires, NIL];

vddWires: Core.Wire ← RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];

vdd: Core.CellType ← RTTestUtil.CreateRecordCell["vdd", vddWires, vddWires, NIL];

gndWires: Core.Wire ← RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];

gnd: Core.CellType ← RTTestUtil.CreateRecordCell["gnd", gndWires, gndWires, NIL];

nandWires: Core.Wire ← RTTestUtil.CreateWire[LIST["InA", "InB", "Out", "Vdd", "Gnd"]];

nand: Core.CellType ← RTTestUtil.CreateRecordCell["NAND", nandWires, nandWires, NIL];

invWires: Core.Wire ← RTTestUtil.CreateWire[LIST["In", "Out", "Vdd", "Gnd"]];

inverter: Core.CellType ← RTTestUtil.CreateRecordCell["Inverter", invWires, invWires, NIL];

pubWires: Core.Wire ← RTTestUtil.CreateWire[LIST["InA", "Out", "Vdd", "Gnd"]];

privateWires: Core.Wire ← RTTestUtil.CreateWire[LIST["NOut"]];

internWires: Core.Wire ← RTTestUtil.UnionWire[pubWires, privateWires];

nandInst: CoreClasses.CellInstance ← RTTestUtil.CreateInstance[LIST["InA", "Vdd", "NOut", "Vdd", "Gnd"], nand, "nandInst", internWires];

invInst: CoreClasses.CellInstance ← RTTestUtil.CreateInstance[LIST["NOut", "Out", "Vdd", "Gnd"], inverter, "invInst", internWires];

SCTest: Core.CellType ← RTTestUtil.CreateRecordCell["SCTest", pubWires, internWires, LIST[nandInst, invInst]];

CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "InA"], SC.sideProp, SC.bottomSideValue];

CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Out"], SC.sideProp, SC.leftSideValue];

CoreProperties.PutCellInstanceProp[nandInst, SC.rowProp, NEW[INT ← 1]];

CoreProperties.PutCellInstanceProp[invInst, SC.rowProp, NEW[INT ← 2]];

[] ← CoreDirectory.RegisterLibrary[coreLibrary, libName];

[] ← CoreDirectory.Insert[coreLibrary, "NAND", nand, TRUE];

[] ← CoreDirectory.Insert[coreLibrary, "Inverter", inverter, TRUE];

[] ← CoreDirectory.Insert[coreLibrary, "feedthru", feedthru, TRUE];

[] ← CoreDirectory.Insert[coreLibrary, "vdd", vdd, TRUE];

[] ← CoreDirectory.Insert[coreLibrary, "gnd", gnd, TRUE];

PWCore.SetGet[nand, libDesign];

PWCore.SetGet[inverter, libDesign];

PWCore.SetGet[feedthru, libDesign];

PWCore.SetGet[vdd, libDesign];

PWCore.SetGet[gnd, libDesign];

CoreProperties.PutCellTypeProp[on: nand, prop: scCutSet, value: $T];

CoreProperties.PutCellTypeProp[on: nand, prop: scCutSet, value: $T];

IF debug THEN {

RETURN [SCTest];

END;