SCMacros.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Preas, July 11, 1986 10:15:48 am PDT
Last Edited by: Preas August 14, 1986 4:32:44 pm PDT
Last Edited by: Louis Monier December 9, 1986 7:28:49 pm PST
Last Edited by: Bryan Preas October 31, 1986 2:52:07 pm PST
DIRECTORY CD, CDSymbolicObjects, Core, CoreGeometry, CoreOps, CoreProperties, PWCore, PWPins, Rope, RTCoreUtil, SC, SCSmash, SCUtil, Sinix, Sisyph;
SCMacros:
CEDAR
PROGRAM
IMPORTS CD, CDSymbolicObjects, CoreGeometry, CoreOps, CoreProperties, PWCore, PWPins, RTCoreUtil, SC, SCSmash, SCUtil, Sisyph
= BEGIN
SCLayoutAtom: ATOM ← PWCore.RegisterLayoutAtom[$SC, StandardCellLayout, StandardCellDecorate, StandardCellAttibutes];
-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.
StandardCellLayout: PWCore.LayoutProc = {
result: SC.Result;
hMaterial: Rope.ROPE ← "metal";
vMaterial: Rope.ROPE ← "metal2";
rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle ← SC.CreateHandle[cellType, RTCoreUtil.defaultFlatten, libName, rules];
SC.InitialPlace[handle, RTCoreUtil.GetCoreNumProp[cellType, SC.rowProp]];
SC.SAPlaceImprove[handle: handle,
saParms: SC.SAPlaceInit[handle, SCUtil.GetCoreInvestmentProp[cellType, SC.investmentProp]]];
SC.GlobalRoute[handle];
SC.PosImprove[handle, 2];
SC.OrientImprove[handle, 2];
SCSmash.CheckFts[handle];
SCSmash.CheckExits[handle];
result ← SC.DetailRoute[handle];
SCUtil.CheckExports[result];
SC.Destroy[handle];
RETURN[result.object]
};
SmashPins:
PROC [wire: Core.Wire] = {CoreGeometry.PutPins[extractMode.decoration, wire,
NIL]};
StandardCellDecorate:
PUBLIC PWCore.DecorateProc = {
EachPublicPin: PWPins.InstanceEnumerator = {
name: Rope.ROPE ← CDSymbolicObjects.GetName[inst];
wire: Core.Wire ← CoreOps.FindWire[cellType.public, name];
pins: LIST OF CD.Instance;
IF wire=NIL THEN RETURN;
pins ← CoreGeometry.GetPins[extractMode.decoration, wire];
CoreGeometry.PutPins[extractMode.decoration, wire, CONS [inst, pins]];
};
CoreOps.VisitRootAtomics[cellType.public, SmashPins];
CoreGeometry.PutIR[extractMode.decoration, cellType, CD.InterestRect[obj]];
[] ← PWPins.EnumerateEdgePins[obj, EachPublicPin];
};
-- Puts as property on public wires their side
StandardCellAttibutes: PWCore.AttributesProc = {
-- [cellType: Core.CellType]
FindSideForEachPin: CoreGeometry.EachWirePinProc = {
[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL ← FALSE]
PushPropOnAtomic:
PROC [wire: Core.Wire] ~ {
CoreProperties.PutWireProp[wire, SC.sideProp, ref];
};
ref:
REF ←
SELECT side
FROM
bottom => SC.bottomSideValue,
top => SC.topSideValue,
right => SC.rightSideValue,
left => SC.leftSideValue,
ENDCASE => SC.noSideValue;
IF wire.size=0 THEN CoreProperties.PutWireProp[wire, SC.sideProp, ref]
ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic];
};
decoration: CoreGeometry.Decoration ← Sisyph.mode.decoration;
IF CoreGeometry.HasIR[decoration, cellType]
THEN
[] ← CoreGeometry.EnumerateWireSides[decoration, cellType, FindSideForEachPin];
};
technologyKey: ATOM ← $cmosB; -- $cmosA or $cmosB
libName: Rope.ROPE ← "CMOSB";
extractMode: Sinix.Mode ← PWCore.extractMode;
END.