SCImpl.mesa SCImpl.mesa
Copyright © 1985, 1986 by Xerox Corporation. All rights reserved.
Bryan Preas, August 14, 1986 5:07:05 pm PDT
Last Edited by: Bryan Preas December 15, 1986 2:14:16 pm PST
DIRECTORY
CD, CDSimpleRules, CDSymbolicObjects, Core, CoreGeometry, CoreOps, CoreProperties, Process, PWCore, PWPins, Rope, Route, RTBasic, RTCoreUtil, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil, Sinix, Sisyph;
SCImpl: CEDAR PROGRAM
IMPORTS CD, CDSimpleRules, CDSymbolicObjects, CoreGeometry, CoreOps, CoreProperties, Process, PWCore, PWPins, Route, RTCoreUtil, RTBasic, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCWidthUtil, SCUtil, Sisyph
EXPORTS SC
SHARES SC = {
debug: BOOLEAN ← FALSE;
Errors
Error: PUBLIC ERROR[errorType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;
Signal: PUBLIC SIGNAL[signalType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;
Design Rules
CreateDesignRules: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, properties: SC.Properties ← NIL] RETURNS [designRules: SC.DesignRules] =
Define the standard cell design rules. technologyKey values are predefinded for now. horizLayer, vertLayer should be "poly", "metal" or "metal2".
BEGIN
hLayer, vLayer: SC.Layer;
designRules ← NEW[SC.DesignRulesRec];
designRules.technology ← CD.FetchTechnology[technologyKey];
hLayer ← CDSimpleRules.GetLayer[technologyKey, horizLayer];
vLayer ← CDSimpleRules.GetLayer[technologyKey, vertLayer];
designRules.horizLayer ← horizLayer;
designRules.vertLayer ← vertLayer;
designRules.rowRules ← Route.CreateDesignRules[technologyKey, hLayer, vLayer, rowDirection, properties];
designRules.sideRules ← Route.CreateDesignRules[technologyKey, hLayer, vLayer, RTBasic.OtherDirection[rowDirection], properties];
END;
Standard Cell Handles and Results
CreateHandle: PUBLIC PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE, designRules: SC.DesignRules, name: Rope.ROPE, properties: SC.Properties ← NIL] RETURNS [handle: SC.Handle] =
Create a standard cell design. The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition.
BEGIN
parms: SCPrivate.Parms ← NARROW[NEW[SCPrivate.ParmsRec], SCPrivate.Parms];
IF designRules = NIL THEN SC.Signal[callingError, "No design rules."];
IF cellType = NIL THEN SC.Signal[callingError, "No Core cell type."];
handle ← NEW[SC.HandleRec];
handle.name ← IF name # NIL THEN name ELSE CoreOps.GetCellTypeName[cellType];
handle.rules ← designRules;
handle.properties ← properties;
handle.coreCellType ← cellType;
parms.libName ← libName;
handle.parms ← parms;
set up the layout data
IF ~SCPrivate.SetUpLayout[handle, cellType] THEN
SC.Signal[callingError, "Unable to construct layout data"];
set up the structure data
IF ~SCPrivate.GetStructure[handle, cellType, flattenCellType] THEN
SC.Signal[callingError, "Unable to construct structure data"];
END;
Standard Cell Optimization and Construction
InitialPlace: PUBLIC PROC [handle: SC.Handle, numRows: NAT ← 0] = {
Determine an initial placement for the instances.
layoutData: SCPrivate.LayoutData ← NARROW[handle.layoutData];
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCSmash.RemoveSmash[handle];
SCPlaceUtil.ClrCurPlac[handle, TRUE];
SCChanUtil.InitChanWidths[handle];
SCInitialPlace.PrePlace[handle: handle, numRows: numRows, routingFactor: 1.8, initialized: TRUE];
SCInitialPlace.RowInit[handle];
SCInitialPlace.PosInit[handle];
[layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] ← SCRowUtil.FindMaxRow[handle];
SCWidthUtil.AllChanWidths[handle, areaFom];
SCInstUtil.AsgnChanPos[handle];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
[] ← SCUtil.WriteResults["End initial placement\n initial size: ", handle, 0];
Process.SetPriority[p]};
PosImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the positions of instances whithin rows.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.PosImprove[handle, areaFom, maxCycles];
Process.SetPriority[p]};
OrientImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the orientation of instances .
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.OrientImprove[handle, areaFom, maxCycles];
Process.SetPriority[p]};
SAInitialPlace: PUBLIC PROC [handle: SC.Handle, seed: INT] RETURNS [initialResult: SC.SAInitialResult] = {
Initialize for simulated annealing improvement.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
initialResult ← SCPrivate.SAInitialPlace[handle, seed];
Process.SetPriority[p]};
SAGetParms: PUBLIC PROC [handle: SC.Handle, initialResult: SC.SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SC.SAParms] = {
determine parameters for simulated placement.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
saParms ← SCPrivate.SAGetParms[handle, initialResult, cellType];
Process.SetPriority[p]};
SAPlaceImprove: PUBLIC PROC [handle: SC.Handle, saParms: SC.SAParms, seed: INT] = {
Improve the placement for the instances by simulated annealing.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.SAPlaceImprove[handle, saParms, seed];
Process.SetPriority[p]};
GlobalRoute: PUBLIC PROC [handle: SC.Handle] = {
Determine strategic paths for the wiring that must cross cell rows.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCSmash.RemoveSmash[handle];
SCSmash.SmashAllNets[handle, TRUE];
Process.SetPriority[p]};
DetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = {
Determine actual wiring paths.
p: Process.Priority ← Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
result ← SCPrivate.DetailRoute[handle];
Process.SetPriority[p]};
CreateLayout: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, numRows: NAT, cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE ← NIL, name: Rope.ROPE ← NIL, properties: SC.Properties ← NIL] RETURNS [object: CD.Object] = {
Create a standard cell object by performing the above operations
result: SC.Result;
designRules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection, properties];
handle: SC.Handle ← SC.CreateHandle[cellType, flattenCellType, libName, designRules, name, properties];
SC.InitialPlace[handle, 0];
SC.SAPlaceImprove[handle, SC.SAGetParms[handle, SC.SAInitialPlace[handle], cellType]];
SC.GlobalRoute[handle];
result ← SC.DetailRoute[handle];
RETURN [result.object];
};
Destroy: PUBLIC PROC [handle: SC.Handle] ~ {
Remove circular references so garbage collection can work
SCPrivate.DestroyLayout[handle];
SCPrivate.DestroyStructure[handle];
SCUtil.DestroyRules[handle];
SCUtil.DestroyParms[handle];
handle.name ← NIL;
handle.coreCellType ← NIL;
handle.properties ← NIL};
-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.
StandardCellLayout: PUBLIC PWCore.LayoutProc = {
result: SC.Result;
saParms: SC.SAParms;
initialResult: SC.SAInitialResult;
hMaterial: Rope.ROPE ← "metal";
vMaterial: Rope.ROPE ← "metal2";
rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle ← SC.CreateHandle[cellType, RTCoreUtil.defaultFlatten, libName, rules];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
initialResult ← SC.SAInitialPlace[handle];
saParms ← SC.SAGetParms[handle, initialResult, cellType];
SC.SAPlaceImprove[handle: handle, saParms: saParms];
SC.GlobalRoute[handle];
SC.PosImprove[handle, 2];
SC.OrientImprove[handle, 2];
SCSmash.CheckFts[handle];
SCSmash.CheckExits[handle];
result ← SC.DetailRoute[handle];
SCUtil.CheckExports[result];
SC.Destroy[handle];
RETURN[result.object]
};
SmashPins: PROC [wire: Core.Wire] = {CoreGeometry.PutPins[extractMode.decoration, wire, NIL]};
StandardCellDecorate: PUBLIC PWCore.DecorateProc = {
EachPublicPin: PWPins.InstanceEnumerator = {
name: Rope.ROPE ← CDSymbolicObjects.GetName[inst];
wire: Core.Wire ← CoreOps.FindWire[cellType.public, name];
pins: LIST OF CD.Instance;
IF wire=NIL THEN RETURN;
pins ← CoreGeometry.GetPins[extractMode.decoration, wire];
CoreGeometry.PutPins[extractMode.decoration, wire, CONS [inst, pins]];
};
CoreOps.VisitRootAtomics[cellType.public, SmashPins];
CoreGeometry.PutIR[extractMode.decoration, cellType, CD.InterestRect[obj]];
[] ← PWPins.EnumerateEdgePins[obj, EachPublicPin];
};
-- Puts as property on public wires their side
StandardCellAttibutes: PUBLIC PWCore.AttributesProc = {-- [cellType: Core.CellType]
FindSideForEachPin: CoreGeometry.EachWirePinProc = {
[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL ← FALSE]
PushPropOnAtomic: PROC [wire: Core.Wire] ~ {
CoreProperties.PutWireProp[wire, SC.sideProp, ref];
};
ref: REF ← SELECT side FROM
bottom => SC.bottomSideValue,
top => SC.topSideValue,
right => SC.rightSideValue,
left => SC.leftSideValue,
ENDCASE => SC.noSideValue;
IF wire.size=0 THEN CoreProperties.PutWireProp[wire, SC.sideProp, ref]
ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic];
};
decoration: CoreGeometry.Decoration ← Sisyph.mode.decoration;
IF CoreGeometry.HasIR[decoration, cellType] THEN
[] ← CoreGeometry.EnumerateWireSides[decoration, cellType, FindSideForEachPin];
};
SCLayoutAtom: ATOM ← PWCore.RegisterLayoutAtom[$SC, StandardCellLayout, StandardCellDecorate, StandardCellAttibutes];
technologyKey: ATOM ← $cmosB;  -- $cmosA or $cmosB
libName: Rope.ROPE ← "CMOSB";
extractMode: Sinix.Mode ← PWCore.extractMode;
Properties
numRows: PUBLIC ATOM ← $numRows;
Used to specify the number of rows for a standard cell assembly. Should be a property on Core cellType being laid out
sideProp: PUBLIC ATOM ← $Side;
bottomSideValue: PUBLIC ATOM ← $bottom;
rightSideValue: PUBLIC ATOM ← $right;
topSideValue: PUBLIC ATOM ← $top;
leftSideValue: PUBLIC ATOM ← $left;
noSideValue: PUBLIC ATOM ← $none;
Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire
rowProp: PUBLIC ATOM ← $Row;
Used to specify the row on which a logic cell is to be placed. rowProp and and integer row number should be a property/value on a locig cell insatance
positionProp: PUBLIC ATOM ← $Position;
Used to specify the position of a logic within a row or of an public pin on a side. May be used on public wire or a logic cell instance.
leftPowerProp: PUBLIC ATOM ← $LeftPower;
rightPowerProp: PUBLIC ATOM ← $RightPower;
Used to specify the side on which power busses are to be placed. May be used on 0, 1 or 2 public wires.
investmentProp: PUBLIC ATOM ← $Investment;
veryLongValue: PUBLIC ATOM ← $veryLong;
longValue: PUBLIC ATOM ← $long;
mediumValue: PUBLIC ATOM ← $medium;
shortValue: PUBLIC ATOM ← $short;
veryShortValue: PUBLIC ATOM ← $veryShort;
Used to specify the investment to make in placement.
t0SA: PUBLIC ATOM ← $t0SA;
alphaSA: PUBLIC ATOM ← $alphaSA;
eqVarLimitSA: PUBLIC ATOM ← $eqVarLimitSA;
fzVarLimitSA: PUBLIC ATOM ← $fzVarLimitSA;
eqTabSizeSA: PUBLIC ATOM ← $eqTabSizeSA;
fzTabSizeSA: PUBLIC ATOM ← $fzTabSizeSA;
Used to specify simulated aneealing partameters to be used for placement
bottomMaxExits: PUBLIC ATOM ← $BottomMaxExits;
rightMaxExits: PUBLIC ATOM ← $RightMaxExits;
topMaxExits: PUBLIC ATOM ← $TopMaxExits;
leftMaxExits: PUBLIC ATOM ← $LeftMaxExits;
Used to specify the maximum number or publics on a side.
bottomExitSpacing: PUBLIC ATOM ← $BottomExitSpacing;
rightExitSpacing: PUBLIC ATOM ← $RightExitSpacing;
topExitSpacing: PUBLIC ATOM ← $TopExitSpacing;
leftExitSpacing: PUBLIC ATOM ← $LeftExitSpacing;
Used to specify the HINT for publics spacing on a side.
interestingProperties: PUBLIC RTCoreUtil.PropertyKeys ← NEW[RTCoreUtil.PropertyKeysRec[23]];
Cedar does not allow initialization of a sequence in the NEW!
interestingProperties.p[0] ← SC.sideProp;
interestingProperties.p[1] ← SC.rowProp;
interestingProperties.p[3] ← SC.positionProp;
interestingProperties.p[4] ← SC.leftPowerProp;
interestingProperties.p[5] ← SC.rightPowerProp;
interestingProperties.p[6] ← SC.numRows;
interestingProperties.p[7] ← SC.bottomMaxExits;
interestingProperties.p[8] ← SC.rightMaxExits;
interestingProperties.p[9] ← SC.topMaxExits;
interestingProperties.p[10] ← SC.leftMaxExits;
interestingProperties.p[11] ← SC.bottomExitSpacing;
interestingProperties.p[12] ← SC.rightExitSpacing;
interestingProperties.p[13] ← SC.topExitSpacing;
interestingProperties.p[14] ← SC.leftExitSpacing;
interestingProperties.p[15] ← SC.investmentProp;
interestingProperties.p[16] ← SC.numRows;
interestingProperties.p[17] ← SC.t0SA;
interestingProperties.p[18] ← SC.alphaSA;
interestingProperties.p[19] ← SC.eqVarLimitSA;
interestingProperties.p[20] ← SC.fzVarLimitSA;
interestingProperties.p[21] ← SC.eqTabSizeSA;
interestingProperties.p[22] ← SC.fzTabSizeSA;
Used to specify all the properties that are interesting to SC
}.