-- File: ECCLogic - Created by SETAR 21-May-86 10:58:40

DIRECTORY
CD,
CDIO,
Core,
CoreClasses,
CoreProperties,
Rope,
RTTestUtil,
ECCLogicOps;

ECCLogic: CEDAR PROGRAM

IMPORTS CDIO, CoreProperties, RTTestUtil, ECCLogicOps
EXPORTS RTTestUtil, ECCLogicOps =

BEGIN OPEN RTTestUtil;

CellInstance: TYPE = CoreClasses.CellInstance;

ct: PUBLIC ECCLogicOps.CellTypeArray;

InitializeTypes: PROC [libDesign: CD.Design] = {
c1IV00BWires: Core.Wire ← CreateWire[LIST["I", "X", "Vdd", "Gnd"]];
c1LT01AWires: Core.Wire ← CreateWire[LIST["Q", "NQ", "D", "NCK", "Vdd", "Gnd"]];
c1XR01BWires: Core.Wire ← CreateWire[LIST["X", "I1XA", "I2XB", "Vdd", "Gnd"]];
c1IV00AWires: Core.Wire ← CreateWire[LIST["I", "X", "Vdd", "Gnd"]];
c1AN04AWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "IXC", "IXD", "Vdd", "Gnd"]];
c1NA02BWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "Vdd", "Gnd"]];
c1NO02AWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "Vdd", "Gnd"]];
c1NA04AWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "IXC", "IXD", "X", "Vdd", "Gnd"]];
c1AN02AWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "Vdd", "Gnd"]];
c1NA02AWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "Vdd", "Gnd"]];
c1AN02BWires: Core.Wire ← CreateWire[LIST["IXA", "IXB", "X", "Vdd", "Gnd"]];
ct[c1IV00B] ← CreateRecordCell["C1IV00B", c1IV00BWires, c1IV00BWires, NIL, NIL, libDesign];
ct[c1LT01A] ← CreateRecordCell["C1LT01A", c1LT01AWires, c1LT01AWires, NIL, NIL, libDesign];
ct[c1XR01B] ← CreateRecordCell["C1XR01B", c1XR01BWires, c1XR01BWires, NIL, NIL, libDesign];
ct[c1IV00A] ← CreateRecordCell["C1IV00A", c1IV00AWires, c1IV00AWires, NIL, NIL, libDesign];
ct[c1AN04A] ← CreateRecordCell["C1AN04A", c1AN04AWires, c1AN04AWires, NIL, NIL, libDesign];
ct[c1NA02B] ← CreateRecordCell["C1NA02B", c1NA02BWires, c1NA02BWires, NIL, NIL, libDesign];
ct[c1NO02A] ← CreateRecordCell["C1NO02A", c1NO02AWires, c1NO02AWires, NIL, NIL, libDesign];
ct[c1NA04A] ← CreateRecordCell["C1NA04A", c1NA04AWires, c1NA04AWires, NIL, NIL, libDesign];
ct[c1AN02A] ← CreateRecordCell["C1AN02A", c1AN02AWires, c1AN02AWires, NIL, NIL, libDesign];
ct[c1NA02A] ← CreateRecordCell["C1NA02A", c1NA02AWires, c1NA02AWires, NIL, NIL, libDesign];
ct[c1AN02B] ← CreateRecordCell["C1AN02B", c1AN02BWires, c1AN02BWires, NIL, NIL, libDesign];
};

CreateCore: PUBLIC PROC [libName: Rope.ROPE] RETURNS [Core.CellType] = BEGIN
libDesign: CD.Design ← CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];
instList: LIST OF CellInstance ← NIL;
ECCLogic: Core.CellType;
pubWires: Core.Wire ← CreateWire[ECCLogicOps.MakepubWires1[]];
internWires: Core.Wire ← RTTestUtil.UnionWire[pubWires, CreateWire[ECCLogicOps.MakeinternWires1[]]];
InitializeTypes[libDesign];
instList ← AppendInstList[instList, ECCLogicOps.MakeInsts2[internWires]];
instList ← AppendInstList[instList, ECCLogicOps.MakeInsts3[internWires]];
instList ← AppendInstList[instList, ECCLogicOps.MakeInsts4[internWires]];
instList ← AppendInstList[instList, ECCLogicOps.MakeInsts5[internWires]];
ECCLogic ← CreateRecordCell["ECCLogic", pubWires, internWires, instList];
CoreProperties.PutWireProp[internWires[762], $Power];
CoreProperties.PutWireProp[internWires[763], $Power];
RETURN[ECCLogic];
END;

END.