DIRECTORY
CD, CDCells, CDIO, Core, CoreClasses, CoreCreate, CoreOps, D2Orient, PWCore, Rope, RTBasic, RTTestUtil, TerminalIO;
RTTestUtilImpl:
CEDAR
PROGRAM
IMPORTS CDCells, CDIO, CoreClasses, CoreCreate, CoreOps, PWCore, RTBasic, TerminalIO
EXPORTS RTTestUtil =
CreateInstance:
PUBLIC
PROC [actual:
LIST
OF Rope.
ROPE, type: Core.CellType, name: Rope.
ROPE, internalWires: Core.Wire, props: Core.Properties ←
NIL]
RETURNS [instance: CoreClasses.CellInstance] = {
create a cell instance rec
actualWire: Core.Wire ← BindWire[actual, internalWires];
instance ← CoreClasses.CreateInstance[actualWire, type, name, props]};
CreateRecordCell:
PUBLIC
PROC [name: Rope.
ROPE, publicWires: Core.Wire, internalWires: Core.Wire ←
NIL, instances: CoreClasses.CellInstances ←
NIL, props: Core.Properties ←
NIL, libDesign:
CD.Design]
RETURNS [cellType: Core.CellType] = {
create a cell instance rec
cellType ← CoreClasses.CreateRecordCell[publicWires, internalWires, instances, name, props];
IF libDesign # NIL THEN PWCore.SetGet[cellType, libDesign]};
CreateWire:
PUBLIC
PROC [ropeList:
LIST
OF Rope.
ROPE]
RETURNS [wire: Core.Wire] ~ {
lowr: LIST OF CoreCreate.WR ← ConvertToWR[ropeList];
wire ← CoreCreate.WireList[lowr]};
AppendInstList:
PUBLIC
PROC [l1, l2: CoreClasses.CellInstances]
RETURNS[val: CoreClasses.CellInstances] = {
z: CoreClasses.CellInstances ← NIL;
val ← l2;
IF l1 = NIL THEN RETURN[val];
val ← CONS[l1.first, val];
z ← val;
UNTIL (l1 ← l1.rest) =
NIL
DO
z.rest ← CONS[l1.first, z.rest];
z ← z.rest;
ENDLOOP;
RETURN[val];
};
AppendRopeList:
PUBLIC
PROC [l1, l2:
LIST
OF Rope.
ROPE]
RETURNS[val: LIST OF Rope.ROPE] = {
z: LIST OF Rope.ROPE ← NIL;
val ← l2;
IF l1 = NIL THEN RETURN[val];
val ← CONS[l1.first, val];
z ← val;
UNTIL (l1 ← l1.rest) =
NIL
DO
z.rest ← CONS[l1.first, z.rest];
z ← z.rest;
ENDLOOP;
RETURN[val];
};
WriteLayout:
PUBLIC
PROC [object:
CD.Object, name: Rope.
ROPE, design:
CD.Design] =
Write a standard cell object to a CND design
BEGIN
[] ← CDCells.IncludeOb[design: design,
cell: NIL, ob: object, trans: [off: [0, 0], orient: original],
mode: doit];
IF ~
CDIO.WriteDesign[design, name]
THEN
TerminalIO.PutRope["Error: design not written\n"];
END;
BindWire:
PROC [actual:
LIST
OF Rope.
ROPE, internalWires: Core.Wire]
RETURNS [actualWire: Core.Wire] = {
do wire binding by name
reverseWireList: LIST OF CoreCreate.WR ← NIL;
newWireList: LIST OF CoreCreate.WR ← NIL;
FOR rl:
LIST
OF Rope.
ROPE ← actual, rl.rest
UNTIL rl=
NIL
DO
r: Rope.ROPE ← rl.first;
index: INT ← CoreOps.GetWireIndex[internalWires, r];
IF index < 0 THEN RTBasic.Error[callingError, NIL];
reverseWireList ← CONS[internalWires[index], reverseWireList];
ENDLOOP;
FOR rl:
LIST
OF CoreCreate.
WR ← reverseWireList, rl.rest
UNTIL rl=
NIL
DO
newWireList ← CONS[rl.first, newWireList];
ENDLOOP;
actualWire ← CoreCreate.WireList[newWireList];
};
UnionWire:
PUBLIC
PROC [wire1, wire2: Core.Wire, name: Rope.
ROPE ←
NIL, props: Core.Properties ←
NIL]
RETURNS [union: Core.Wire] ~ {
Creates a new structured wire of size wire1.size+wire2.size, with corresponding name and properties
RETURN [CoreOps.UnionWire[wire1, wire2]]};
ConvertToWR:
PROC [list:
LIST
OF Rope.
ROPE]
RETURNS[wrl:
LIST
OF CoreCreate.
WR ←
NIL] = {
reverseWireList: LIST OF CoreCreate.WR ← NIL;
UNTIL list =
NIL
DO
reverseWireList ← CONS[list.first, reverseWireList];
list ← list.rest;
ENDLOOP;
UNTIL reverseWireList =
NIL
DO
wrl ← CONS[reverseWireList.first, wrl];
reverseWireList ← reverseWireList.rest;
ENDLOOP;
RETURN[wrl];
}; -- of ConvertToWR
END.