MyCellModule.mesa
Copyright © 1987 by Xerox Corporation. All rights reserved.
Monier, January 5, 1987 8:15:51 pm PST
Gasbarro, January 23, 1987 2:17:39 pm PST
Barth, February 2, 1987 1:13:06 pm PST
DIRECTORY CDCommandOps, CDSequencer, Core, CoreCreate, CoreFlat, Ports, Rope, Rosemary, RosemaryUser, Sisyph;
MyCellModule: CEDAR PROGRAM
IMPORTS CDCommandOps, CDSequencer, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, Sisyph
= BEGIN
This file contains templates for attaching behavior and tests to cell types generated by program or by extraction. The behavioral template should not be used when the cell type is used more than once in a design and the cell type is saved in a cache using CoreIO.
Binding
MyCellPhA, MyCellPhB, Vdd, Gnd: NAT ← LAST[NAT];
MyCellInitPortIndicies: PROC [p: Core.Wire] ~ {
[up to 12 signals] ← Ports.PortIndexes[p, up to 12 quoted signals];
[Vdd, Gnd] ← Ports.PortIndexes[p, "Vdd", "Gnd"];
};
Structure
MyCell: PUBLIC PROC [arguments] RETURNS [cellType: CoreCreate.CellType] = {
public: Core.Wire ← CoreCreate.Wires[
"simpleWire",
CoreCreate.Seq["bus", bitsInBus],
"Vdd", "Gnd"];
cellType ← CoreClasses.CreateUnspecified[name: "MyCell", public: public];
MyCellInitPortIndicies[public];
IPList[public, LIST[MyCellPhA, MyCellPhB], b];
};
Test
InitializeTest: PROC ~ {
CDSequencer.ImplementCommand[key: $MyCellExtractAndSimulate, proc: MyCellExtractAndSimulate, queue: doQueue];
CDCommandOps.RegisterWithMenu[menu: $ProgramMenu, entry: "Simulate MyCell", key: $MyCellExtractAndSimulate];
RosemaryUser.RegisterTestProc["MyCellTest", MyCellTest]; 
};
MyCellExtractAndSimulate: PROC [comm: CDSequencer.Command] ~ {
cellType: Core.CellType ← Sisyph.ExtractSchematicByName["MyCell.sch", Sisyph.Create[comm.design]];
public: Core.Wire ← cellType.public;
MyCellInitPortIndicies[public];
IPList[public, LIST[MyCellPhA, MyCellPhB], b];
MyCellSimulate[cellType];
};
MyCellCreateAndSimulate: PROC ~ {
cellType: Core.CellType ← MyCell[arguments];
MyCellSimulate[cellType];
};
MyCellSimulate: PROC [cellType: Core.CellType] ~ {
public: Core.Wire ← cellType.public;
ITDList[public, LIST[inputs], force];
ITDList[public, LIST[outputs], expect];
ITDList[public, LIST[inputs/outputs], none];
[] ← Rosemary.SetFixedWire[cellType.public[Vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[Gnd], L];
[] ← RosemaryUser.TestProcedureViewer[
cellType: cellType,
testButtons: LIST["MyCellTest"],
name: "MyCell Test",
displayWires: RosemaryUser.DisplayPortLeafWires[cellType],
cutSet: CoreFlat.CreateCutSet[labels: LIST["Logic", "LogicMacro", "FSA"]]];
};
MyCellTest: RosemaryUser.TestProc ~ { -- PROC [cellType: Core.CellType, p: Ports.Port, Eval: PROC]
MyCellInitPortIndicies[cellType.public];
p[MyCellPhA].b ← TRUE;
p[MyCellPhB].b ← FALSE;
Eval[];
};
Behavior
MyCellName: Rope.ROPE = Rosemary.Register[roseClassName: "MyCell", init: MyCellInit, evalSimple: MyCellSimple];
MyCellState: TYPE = REF MyCellStateRec;
MyCellStateRec: TYPE = RECORD [
any state: any type];
MyCellInit: Rosemary.InitProc = {
state: MyCellState ← IF oldStateAny#NIL THEN NARROW[oldStateAny] ELSE NEW[MyCellStateRec];
MyCellInitPortIndicies[cellType.public];
stateAny ← state;
};
MyCellSimple: Rosemary.EvalProc = {
state: MyCellState ← NARROW[stateAny];
body of the proc
};
Belongs in Ports
ITDList: PROC [public: CoreCreate.Wire, indicies: LIST OF NAT, initDrive: Ports.Drive] ~ {
FOR l: LIST OF NAT ← indicies, l.rest WHILE l#NIL DO
[] ← Ports.InitTesterDrive[wire: public[l.first], initDrive: initDrive];
ENDLOOP;
};
IPList: PROC [public: CoreCreate.Wire, indicies: LIST OF NAT, levelType: Ports.LevelType, initDrive: Ports.Drive ← none] ~ {
FOR l: LIST OF NAT ← indicies, l.rest WHILE l#NIL DO
[] ← Ports.InitPort[wire: public[l.first], levelType: levelType, initDrive: initDrive];
ENDLOOP;
};
Start Code
InitializeTest[];
END.