RoseTest.cm
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, April 5, 1986 3:47:47 pm PST
Bertrand Serlet June 17, 1986 1:59:37 pm PDT
Core
Run -a PortsImpl
Run -a RosemaryImpl
Run -a SSIImpl
← &AndVdd ← 0;
← &AndGnd ← 1;
← &AndInput ← 2;
← &AndOutput ← 3;
← &ct ← SSI.And[2]
← Ports.InitTesterDrive[wire: &ct.public[&AndInput][0], initDrive: force]
← Ports.InitTesterDrive[wire: &ct.public[&AndInput][1], initDrive: force]
← Ports.InitTesterDrive[wire: &ct.public[&AndOutput], initDrive: none]
← Rosemary.SetFixedWire[&ct.public[&AndVdd], H]
← Rosemary.SetFixedWire[&ct.public[&AndGnd], L]
← &tp ← Ports.CreatePort[&ct.public, TRUE]
-- ← CoreOps.Print[&ct]
-- ← &sim ← Rosemary.InstantiateCellType[&ct, &tp]
-- ← &sim ← Rosemary.InstantiateInstances[&ct, &tp, "JustAboveTransistors"]
← &sim ← Rosemary.InstantiateInstances[&ct, &tp]
← &tp[&AndInput][0].b ← FALSE
← &tp[&AndInput][1].b ← FALSE
← Rosemary.Settle[&sim, NIL]
← &tp[&AndOutput].b -- FALSE
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [[0, ALL[FALSE]], &ct.public[&AndOutput]]]] -- L
← &tp[&AndInput][0].b ← TRUE
← &tp[&AndInput][1].b ← TRUE
← Rosemary.Settle[&sim, NIL]
← &tp[&AndOutput].b -- TRUE
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [[0, ALL[FALSE]], &ct.public[&AndOutput]]]] -- H
← &tp[&AndInput][0].b ← TRUE
← &tp[&AndInput][1].b ← FALSE
← Rosemary.Settle[&sim, NIL]
← &tp[&AndOutput].b -- FALSE
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [[0, ALL[FALSE]], &ct.public[&AndOutput]]]] -- L
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [CoreFlat.ComputePackedPath[&ct, LIST[&ct.data[0]]], &ct.data[0].type.data[0].actual[1]]]] -- H
← &tp[&AndInput][0].b ← FALSE
← &tp[&AndInput][1].b ← TRUE
← Rosemary.Settle[&sim, NIL]
← &tp[&AndOutput].b -- FALSE
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [[0, ALL[FALSE]], &ct.public[&AndOutput]]]] -- L
← Rosemary.WireValue[&sim, NEW [CoreFlat.FlatWireRec ← [CoreFlat.ComputePackedPath[&ct, LIST[&ct.data[0]]], &ct.data[0].type.data[0].actual[1]]]] -- L