<> <> <> <> <<>> DIRECTORY BitOps, Core, CoreCreate; Ports: CEDAR DEFINITIONS = BEGIN <> <> <> <> <> PortList: TYPE = LIST OF Port; Port: TYPE = REF PortRec; <<>> <> <<>> <> <> < [d: Drive _ none, l: Level _ L],>> < [d: Drive _ none, b: BOOL _ FALSE],>> < [ls: LevelSequence _ NIL, dt: SELECT driveType: DriveType FROM>> < [d: Drive _ none],>> < [ds: DriveSequence _ NIL],>> <> < [bs: BoolSequence _ NIL, dt: SELECT driveType: DriveType FROM>> < [d: Drive _ none],>> < [ds: DriveSequence _ NIL],>> <> < [>> <> <> <> < [d: Drive _ none],>> < [ds: DriveSequence _ NIL],>> <> < [>> <> <> <> < [d: Drive _ none],>> < [ds: DriveSequence _ NIL],>> <> < [>> <> <> <> < [d: Drive _ none],>> < [ds: DriveSequence _ NIL],>> <> < [composite: SEQUENCE size: NAT OF Port],>> <> <<>> PortRec: TYPE = RECORD [ levelType: LevelType _ composite, driveType: DriveType _ aggregate, d: Drive _ none, l: Level _ L, b: BOOL _ FALSE, ds: DriveSequence _ NIL, ls: LevelSequence _ NIL, bs: BoolSequence _ NIL, fieldStart: [0..64) _ 0, c: BitOps.BitWord _ BitOps.BitWordZero, lc: BitOps.BitDWord _ BitOps.BitDWordZero, q: BitOps.BitQWord _ BitOps.BitQWordZero, composite: SEQUENCE size: NAT OF Port]; LevelType: TYPE = {l, ls, b, bs, c, lc, q, composite}; DriveType: TYPE = {aggregate, seperate}; Drive: TYPE = { expect, -- allows port to specify expected value none, --from a test proc it means neither driven nor checked; in switch-level it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, force, -- weakest drive level, allows test procs to check if device has tristated driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, infinite -- drive for nodes which have infinite current sources }; Level: TYPE = {L, H, X}; DriveSequence: TYPE = REF DriveSequenceRec; DriveSequenceRec: TYPE = RECORD [drives: PACKED SEQUENCE size: NAT OF Drive]; LevelSequence: TYPE = REF LevelSequenceRec; LevelSequenceRec: TYPE = RECORD [levels: PACKED SEQUENCE size: NAT OF Level]; BoolSequence: TYPE = REF BoolSequenceRec; BoolSequenceRec: TYPE = RECORD [bools: PACKED SEQUENCE size: NAT OF BOOL]; PortData: TYPE = REF PortDataRec; PortDataRec: TYPE = RECORD [ levelType: LevelType, driveType: DriveType, drive: Drive, drives: DriveSequence]; levelTypeNames: ARRAY LevelType OF Core.ROPE; levelNames: ARRAY Level OF Core.ROPE; driveTypeNames: ARRAY DriveType OF Core.ROPE; driveNames: ARRAY Drive OF Core.ROPE; <> FindLevelType: PROC [levelTypeID: Core.ROPE] RETURNS [levelType: LevelType]; FindLevel: PROC [levelID: Core.ROPE] RETURNS [level: Level]; FindDriveType: PROC [driveTypeID: Core.ROPE] RETURNS [driveType: DriveType]; FindDrive: PROC [driveID: Core.ROPE] RETURNS [drive: Drive]; CreatePort: PROC [cellType: Core.CellType, testerPort: BOOL _ FALSE] RETURNS [port: Port]; <> <<>> RenewPort: PROC [cellType: Core.CellType, port: Port, testerPort: BOOL _ FALSE]; <<>> InitPort: PROC [wire: Core.Wire, levelType: LevelType _ b, driveType: DriveType _ aggregate, initDrive: Drive _ none, initDrives: DriveSequence _ NIL] RETURNS [sameWire: Core.Wire]; InitPorts: PROC [ct: Core.CellType, initType: LevelType _ l, initDrive: Drive _ none, n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10: CoreCreate.WR _ NIL]; InitPortList: PROC [ct: Core.CellType, initType: LevelType _ l, initDrive: Drive _ none, ports: LIST OF CoreCreate.WR]; InitTesterDrive: PROC [wire: Core.Wire, initDrive: Drive _ none, initDrives: DriveSequence _ NIL]; <> InitTesterDrives: PROC [ct: Core.CellType, initDrive: Drive _ none, n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10: CoreCreate.WR _ NIL]; InitTesterDriveList: PROC [ct: Core.CellType, initDrive: Drive _ none, ports: LIST OF CoreCreate.WR]; ITDList: PROC [public: Core.Wire, indicies: LIST OF NAT, initDrive: Drive]; IPList: PROC [public: Core.Wire, indicies: LIST OF NAT, levelType: LevelType, initDrive: Drive _ none]; WirePortType: PROC [cellType: Core.CellType, wire: Core.Wire] RETURNS [levelType: LevelType, driveType: DriveType]; PortLeaves: PROC [port: Port] RETURNS [leaves: CARDINAL]; PortIndex: PROC [wire: Core.Wire, name: Core.ROPE] RETURNS [NAT]; PortIndexes: PROC [wire: Core.Wire, n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11: Core.ROPE _ NIL] RETURNS [i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11: NAT _ LAST[NAT]]; CopyPortValue: PROC [from: Port, to: Port]; <> CheckPortValue: PROC [root: Core.Wire, truth: Port, question: Port]; <> <<>> CheckError: SIGNAL [msg: Core.ROPE]; <> EachPortPairProc: TYPE = PROC [onePort: Port, anotherPort: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitPortPair: PROC [onePort: Port, anotherPort: Port, eachPortPair: EachPortPairProc] RETURNS [quit: BOOL]; <> EachWirePortPairProc: TYPE = PROC [wire: Core.Wire, port: Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE]; VisitBinding: PROC [wire: Core.Wire, port: Port, eachWirePortPair: EachWirePortPairProc] RETURNS [quit: BOOL]; <> <> ConversionError: SIGNAL; NotL: PROC [a: Level] RETURNS [b: Level]; AndL: PROC [a, b: Level] RETURNS [c: Level]; OrL: PROC [a, b: Level] RETURNS [c: Level]; XorL: PROC [a, b: Level] RETURNS [c: Level]; SumL: PROC [a, b, c: Level] RETURNS [carry, s: Level]; NotLS: PROC [a, b: LevelSequence]; CopyLS: PROC [from, to: LevelSequence]; SetLS: PROC [seq: LevelSequence, level: Level]; LSToRope, LevelSequenceToRope: PROC [container: LevelSequence, size: NAT _ 0, base: NAT _ 16] RETURNS [val: Core.ROPE]; LSToC: PROC [ls: LevelSequence] RETURNS [c: CARDINAL]; <> <<>> LSToLC: PROC [ls: LevelSequence] RETURNS [lc: LONG CARDINAL]; <> <<>> LCToLS: PROC [lc: LONG CARDINAL, ls: LevelSequence]; <> <<>> END.