Parsley.mesa
Copyright
©
1986 by Xerox Corporation. All rights reserved.
Barth, October 10, 1986 3:09:24 pm PDT
DIRECTORY
Core;
Parsley
:
CEDAR
DEFINITIONS
=
BEGIN
Theory
Analyzes synchronous sequential circuits.
Types
ROPE
:
TYPE
= Core.
ROPE
;
Value Context
ValueProc:
TYPE
=
PROC
[valueSet: Ports.LevelSequence];
ValueSetProc:
TYPE
=
PROC
[wire: Core.Wire, eachValueSet: ValueProc];
Enumerates the valid states of the wires.
NonOverlap
: ValueSetProc;
public: Clock[n], nClock[n]
Enumerates the valid states of the wires.
Critical Path
CriticalPaths
:
PROC
[root: Core.CellType, eachPath: CriticalPathProc, cutSet: CoreFlat.CutSet ←
NIL
];
Enumerates the critical paths in decreasing delay order.
CriticalPathProc:
TYPE
=
PROC
[path: CombinationalPath, delay:
REAL
];
END
.