First, check the tri-state gate. Note the pipeline delays for the various paths. We need an extra cycle of reset at the beginning; I don't know why that is...
00 0 0 1 | xx x
00 0 0 1 | xx x
00 0 0 0 | xx 1
00 0 1 x | 0x 0
00 1 1 x | 01 1
00 1 1 x | 01 0
Next fool with the registers.
01 1 1 x | 01 0
10 1 1 x | 01 0
11 1 1 x | 11 0
00 1 1 x | 11 0
00 1 1 x | 11 0
00 1 1 x | 00 0
Finally make a mistake on purpose so we can see how that goes ... the 00 0 output should really be 01 0.