NETran: circuit[gate, source, drain, bulk | l _ 2, w _ 8, as _ 240, ad _ 240, ps _ 80, pd _ 80, dWFact _ 1] = {fet: MosFet[gate, source, drain, bulk |Lm _ l*Lambda,Wm _ w*Lambda,As _ as*Lambda*Lambda,Ad _ ad*Lambda*Lambda,Ps _ ps*Lambda,Pd _ pd*Lambda,Vfb_ -1.22980,Na_ 9.885124E+16,Tox_ 295,Lk1_ -5.339235E-02,Wk1_ -7.352594E-02,K20_ 0.280243,Lk2_ 26.254938E-02,Wk2_ -0.524566,Etao_ 4.584877E-03,nEta_ 2.66516,Un_ 558.453,Vo_ 105.205,Lu_ 13.4530,Ecrit_ 4.09776,Lv_ 3.05445,dL_ -0.201643,dW_ -1.60051*dWFact,Xj2 _ 0.4,TDegC _ 25,Cj _ 8.73E-17,Cjm _ 1.10E-16,Pb _ 0.90]}; -- NETranETran: circuit[gate, source, drain | L _ 2, W _ 4, sdExtend _ 0, dWFact _ 1] = {nt: NETran[gate, source, drain, Gnd |l _ L,w _ W,as _ W*sdExtend,ad _ W*sdExtend,ps _ 2*sdExtend+(sdExtend>0)*W,pd _ 2*sdExtend+(sdExtend>0)*W,dWFact _ dWFact]}; -- ETranPETran: circuit[gate, source, drain, bulk |l _ 2, w _ 24, as _ 720, ad _ 720, ps _ 110, pd _ 110, dWFact _ 1] = {fet: MosFet[gate, source, drain, bulk |Lm _ l*Lambda,Wm _ w*Lambda,As _ as*Lambda*Lambda, Ad _ ad*Lambda*Lambda,Ps _ ps*Lambda, Pd _ pd*Lambda,Vfb_ -0.563522,Na_ 1.335061E+16,Tox_ 295,Lk1_ -0.977357,Wk1_ -5.709164E-02,K20_ -2.316437E-02,Lk2_ 2.57879,Wk2_ 3.92364,Etao_ 2.882671E-02,nEta_ 2.29445,Un_ 185.816,Vo_ 19.0121,Lu_ 1.56999,Ecrit_ 8.600,Lv_ 3.53001,dL_ -7.001376E-02,dW_ -1.54116*dWFact,TDegC _ 25,Xj2 _ 0.4,Type _ -1,Cj _ 2.33E-16,Cjm _ 2.95E-16,Pb _ 0.94]}; -- PETranCTran: circuit[gate, source, drain | L _ 2, W _ 4, sdExtend _ 0, dWFact _ 1] = {pt: PETran[gate, source, drain, Vdd |l _ L,w _ W,as _ W*sdExtend,ad _ W*sdExtend,ps _ 2*sdExtend+(sdExtend>0)*W,pd _ 2*sdExtend+(sdExtend>0)*W,dWFact _ dWFact]}; -- CTranNDTran: circuit[gate, source, drain | -- from NMos4.0u25.thyL _ 4, W _ 2, sourceExtension _ 1, drainExtension _ 1, dWFact _ 1]= {fet: MosFet[gate, source, drain, Gnd |Lm _ L*Lambda,Wm _ W*Lambda,As _ sourceExtension*W*Lambda*Lambda, Ad _ drainExtension*W*Lambda*Lambda,Ps _ (2*sourceExtension+W)*Lambda, Pd _ (2*drainExtension+W)*Lambda,Vfb _ -4.24520,Na _ 9.721774E+14,Tox _ 700,Lk1 _ -1.05228,Wk1 _ 2.83468,K20 _ -1.200934E-02,Lk2 _ 6.95809,Wk2 _ -0.802315,Etao _ 2.570121E-02,nEta _ 3.67642,Un _ 848.461,Vo _ 31.6363,Lu _ -0.141426,Ecrit _ 1.05208,Lv _ 26.6670,dL _ 0.550266,dW _ -2.41600*dWFact,TDegC _ Temp,Cj _ 8.73E-17,Cjm _ 2.21E-16,Pb _ 0.90]}; -- NDTranWireCap:  circuit[n | -- l=length, w=width, a=area, p=perimeterlM2 _ 0, wM2 _ 4, aM2 _ 0, pM2 _ 0, -- 2nd layer metallM _ 0, wM _ 3, aM _ 0, pM _ 0,  -- 1rst layer metallP _ 0, wP _ 2, aP _ 0, pP _ 0,  -- polyaG_ 0, pG _ 0, -- poly over thin oxide (if transistor unsimulated)aM2C _ .197E-4pF, pM2C _ .486E-4pF, -- /(uM)^2, /uM, 2nd layer metal to bulkaMC _ .276E-4pF, pMC _ .496E-4pF,  -- 1rst layer metal to bulkaPC _ .628E-4pF, pPC _ .577E-4pF,  -- poly to bulkaGC _ 11.8e-4pF -- poly over thin oxide] = {?: capacitor[n, Gnd] = Lambda*(Lambda*((aM2 + lM2*wM2)*aM2C + (aM + lM*wM)*aMC + (aP + lP*wP)*aPC + aG*aGC) + (pM2 + 2*lM2 + 2*wM2)*pM2C + (pM + 2*lM + 2*wM)*pMC + (pP + 2*lP)*pPC)}; -- WireCapDifCap: circuit[n |lnD _ 0, wnD _ 0, anD _ 0, pnD _ 0, lpD _ 0, wpD _ 0, apD _ 0, ppD _ 0]= {ndc: Diffusion[n, Gnd |a _ (lnD*wnD+anD)*Lambda*Lambda,p _ (2*(lnD+wnD)+pnD)*Lambda,Cj _ 1.5E-4pF, -- /(um)^2Cjm _ 3E-4pF, -- /um of sidewallPb _ 0.90,TDegC _ 25];pdc: Diffusion[n, Gnd |a _ (lpD*wpD + apD)*Lambda*Lambda,p _ (2*(lpD + wpD) + ppD)*Lambda,Cj _ 3.1E-4pF,Cjm _ 3.0E-4pF,Pb _ 0.94,TDegC _ 25]}; -- DifCapWireRes: circuit[nodeA, nodeB |lM2 _ 0, wM2 _ 4,lM _ 0, wM _ 3, lP _ 0, wP _ 2, lnD _ 0, wnD _ 2,lpD _ 0, wpD _ 2,sM2R _ 0.06, -- ohms/squaresMR _ 0.06,sPR _ 3.5, -- polysilicidesnDR _ 35,spDR _ 120] = {R: resistor[nodeA, nodeB] = lM2/wM2*sM2R + lM/wM*sMR + lP/wP*sPR + lnD/wnD*snDR + lpD/wpD*spDR}; -- WireResConRes: circuit[nodeA, nodeB |nM2M _ 0, -- number of parallel 2nd layer metal to 1rst layer metal viasnMP _ 0, -- number of parallel 1rst layer metal to poly contactsnMD _ 0, -- number of parallel 1rst layer metal to diffusion contactsnPD _ 0, -- number of parallel poly to diffusion contacts, buttingcM2MR _ 40, -- ohms/via, 2nd layer metal to 1rst layercMPR _ 4, -- ohms/contact, metal-polysilicidecMDR _ 25, -- ohms/contact, metal-diffusioncPDR _ 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact] = {R: resistor[nodeA, nodeB] = 1/(nM2M/cM2MR + nMP/cMPR + nMD/cMDR + nPD/cPDR)}; -- ConResStray:  circuit[n |aM2 _ 0, pM2 _ 0,aM _ 0, pM _ 0,aP _ 0, pP _ 0,anD _ 0, pnD _ 0,apD _ 0, ppD _ 0,aG _ 0, pG _ 0] = {wireCap: WireCap [n |aM2 _ aM2, pM2 _ pM2,aM _ aM, pM _ pM,aP _ aP, pP _ pP,aG _ aG, pG _ pG];difCap: DifCap [n | anD _ anD, pnD _ pnD, apD _ apD, ppD _ ppD];}; -- Stray  v  File: CMos2.0u25C.thyLast Edited:McCreight, April 2, 1985 6:16:51 pm PSTSweetsun Chen, September 18, 1985 9:36:43 pm PDTsdExtend default set to 0, dWFact added by McCreight, March 7, 1985 12:41:31 pm PSTsdExtend is added by Ted Williams on July 7, 1983  11:48 AMIt is a guessed value to calculate source and drain capacitance, as suggested by McCreight.   Nobody really has a better way.The 0-bias values are taken from ICL's "Report on Process and Electrical Parameters" by Richard Bruce and John Chen, dated 21 Feb 85.  The n+ area and perimeter values in that report are measured, and the p+ area and perimeter values are inherited from I. Bol's MEC "Xerox CMOS Process Specification and Layout Design Rules" memo of February 83.Change Log.Created on June 11, 1983  5:51 PM. Entered parameters extracted by Akis Doganis for CMOS21, run 70, wafer 9, DIE=126-127. (cf. Akis' memo of May 17, 83.); Values for Cj, Cjm, and Pb were calculated from process data provided by RBruce. (SChen)  Added parasitic circuits. (Barth)McCreight, September 15, 1983  to add Stray capacitances from I. Bol's Xerox (ED) CMOS Spec of Feb 83McCreight, October 18, 1983  5:27 PM  to add simulated depletion NMOSTed Williams June 22, 1984  2:08 PM to add new extracted data from Akis Doganis for CSIM model. (CMOS36) Run 120, Wafer 10, DIE=128-127.SChen, October 24, 1984 6:18:37 pm PDT, corrected calculations for Ps/Pd using sdExtension.McCreight, March 5, 1985 3:02:29 pm PSTto cause calculated stray capacitances to agree with Wheeler's microstrip equations for fringing capacitance (Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane, IEEE Transactions on Microwave Theory and Techniques, vol MTT-25, No. 8, August, 1977, pp. 631-647).to cause diffusion capacitances to agree with ICL's Report on Process and Electrical Parameters by R. Bruce and J. Chen, 21 Feb 85.NOTE: The CSIM transistor parameters agree with measured data taken from (CMOS36) Run 120, Wafer 10, DIE=128-127.  This data in turn agrees with the nominal n-channel transconductance in ICL's Report, but is near the minimum p-channel transconductance in that report.  Êù  ˜ Jšœ™šœ™J™'Icode™0—J˜ šÏbœi˜oJ˜ ˜'J˜J˜J˜J˜J˜J˜J˜J˜J˜	J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜Jšœ˜J˜
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