CoreThymeDoc.tioga
Written by: Pradeep Sindhu, April 3, 1986 6:10:44 pm PST
Last Edited by:
Bertrand Serlet July 9, 1986 12:28:19 pm PDT
Pradeep Sindhu, April 29, 1986 1:51:12 am PDT
CORETHYME: CIRCUIT SIMULATION WITHOUT TEARS
CORETHYME: CIRCUIT SIMULATION WITHOUT TEARS
CORETHYME: CIRCUIT SIMULATION WITHOUT TEARS
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
CoreThyme: Circuit Simulation Without Tears
Pradeep Sindhu
User Manual
Release as [DATools]<DATools6.1>CoreThyme>CoreThymeDoc.tioga, .press
© Copyright 1985, 1986 Xerox Corporation. All rights reserved.
Abstract: CORETHYME is a program that translates Core data structures into THYME input, permitting circuit diagrams drawn as schematics to be simulated conveniently. With some additional work it will also be possible to simulate layouts with comparable ease.
Created by: Pradeep Sindhu
Maintained by: Sindhu <Sindhu.pa>, Le Cocq <LeCocq.pa>.
Keywords: Circuit Simulation, Schematics Extraction
XEROX  Xerox Corporation
   Palo Alto Research Center
   3333 Coyote Hill Road
   Palo Alto, California 94304



For Internal Xerox Use Only
Contents
Introduction
CORETHYME Icons
Programming Interface
User Interface
Running CORETHYME
Limitations
Introduction
Anyone who has prepared input for the circuit simulators THYME or SPICE by hand will concede that there are more convenient ways of accomplishing this task. The purpose of CORETHYME is to provide such a convenient method by translating Core data structures to THYME input. Since our new circuit extractors all output Core, schematics and layout may be simulated directly without having to deal with THYME's input language.
The input to CORETHYME is a Core cellType decorated with the information needed to run the THYME simulation. This cellType may have been produced using SISYPH, SinixCMosB, or for that matter constructed directly by program. For the purposes of this document, however, we will assume that the cellType has been obtained by drawing a schematic and extracting it using SISYPH. It is useful to recall that SISYPH schematics are drawn using icons that represent simpler schematics and wires that connect icons together. Icons may have arbitrary geometry, while wires are drawn as collections of connected rectangles (see the SISYPH documentation for more details).
To use CORETHYME, a user first draws his schematic using a mix of the the standard SSI icons and perhaps icons he has defined. He then adds a number of CORETHYME icons to provide signal drive, signal display, and simulation control. Finally, he encapsulates all of these in a ChipNDale cell and simulates it by pointing and clicking. Any parameters needed by THYME, as well as sizes of transistors and other components, etc. are specified in the standard way using satellites and/or expressions.
The remainder of this document provides details. The first section describes CORETHYME icons and how to use them. The following two sections cover the programming and user interfaces, while the last section describes how to run CORETHYME. It is assumed throughout that the reader is familiar with SISYPH and understands the essentials of Core.
CORETHYME Icons
see ElectricalCoreClasses.df
Programming Interface
The programming interface resides in CoreThyme.mesa. It defines three procedures.
InitThyme: PROC [wDir: ROPE] RETURNS [handle: ThymeHandle];
Initializes Thyme.
Translate: PROC [cellType: CellType, outputFile: ROPE];
Translates cellType into a Thyme file and puts the result in outputFile.
Simulate: PROC [inputFile: ROPE, handle: ThymeHandle];
Simulates the circuit specified in inputFile.
User Interface
The user interface for CORETHYME consists of one command called SISYPH Extract and THYME, available via the <space>-O menu. This command takes a selected ChipNDale cell as argument, extracts the cell using SISYPH, translates the resulting cellType into a THYME file and then invokes THYME on that file. The user of course never sees the file unless he explicitly opens it (I'd advise you against it!).
Running CORETHYME
1. Bringover -p [DATools]<DATools6.1>Top>DAUser.df
2. Type Schematics to the Commander.
3. Create a new CMosB design using CDNewCMosB.
4. Do a CDBringover of the file EE.dale (and SSI.dale if you want to draw SSI gates).
Limitations
CORETHYME does not as yet work on layout since we don't have a program to decorate the Core cellType for a layout with the stray capacitance from that layout. Once the decoration program is written it should be relatively straightforward to get CORETHYME to work on layout as well.