File: [Cherry]<Thyme>Cedar5.2>ProcessDefs>CMos2.0u100C.thy
Last Edited by: SChen, October 24, 1984 6:30:26 pm PDT
Last Edited by: McCreight, April 2, 1985 6:17:14 pm PST
NETran: circuit[gate, source, drain, bulk | l ← 2, w ← 8, as ← 240, ad ← 240, ps ← 80, pd ← 80, dWFact ← 1] = {
fet: MosFet[gate, source, drain, bulk |
Lm ← l*Lambda,
Wm ← w*Lambda,
As ← as*Lambda*Lambda,
Ad ← ad*Lambda*Lambda,
Ps ← ps*Lambda,
Pd ← pd*Lambda,
Vfb← -0.710305,
Na← 4.505551E+16,
Tox← 310,
Lk1← -0.340033,
Wk1← 0.193772,
K20← 0.179467,
Lk2← -0.148137,
Wk2← -0.180754,
Etao← 2.541379E-02,
nEta← 3.38740,
Un← 396.157,
Vo← 38.8748,
Lu← 1.000E-06,
Ecrit← 2.15085,
Lv← 3.67376,
dL← -0.136870,
dW← -1.20537*dWFact,
Xj2 ← 0.4,
TDegC ← 100,
Cj ← 5.27E-17,
Cjm ← 6.64E-17,
Pb ← 1.1265
]
}; -- NETran
ETran: circuit[gate, source, drain |
L ← 2,
W ← 4, sdExtend ← 0, dWFact ← 1] = {
sdExtend default set to 0, dWFact added by McCreight, March 7, 1985 12:41:31 pm PST
sdExtend is added by Ted Williams on July 7, 1983 11:48 AM
It is a guessed value to calculate source and drain capacitance, as suggested by McCreight. Nobody really has a better way.
nt: NETran[gate, source, drain, Gnd |
l ← L,
w ← W,
as ← W*sdExtend,
ad ← W*sdExtend,
ps ← 2*sdExtend+(sdExtend>0)*W,
pd ← 2*sdExtend+(sdExtend>0)*W,
dWFact ← dWFact
]
}; -- ETran
PETran: circuit[gate, source, drain, bulk |
l ← 2, w ← 24, as ← 720, ad ← 720, ps ← 110, pd ← 110, dWFact ← 1] = {
fet: MosFet[gate, source, drain, bulk |
Lm ← l*Lambda,
Wm ← w*Lambda,
As ← as*Lambda*Lambda,
Ad ← ad*Lambda*Lambda,
Ps ← ps*Lambda,
Pd ← pd*Lambda,
Vfb← -0.264791,
Na← 1.133016E+16,
Tox← 310,
Lk1← -1.11216,
Wk1← -3.509532E-02,
K20← -5.339097E-02,
Lk2← 1.32741,
Wk2← 1.41077,
Etao← 3.449609E-02,
nEta← 2.61475,
Un← 135.857,
Vo← 18.9479,
Lu← 0.516323,
Ecrit← 9.55550,
Lv← 3.51166,
dL← -8.836786E-02,
dW← -1.19803*dWFact,
TDegC ← 100,
Xj2 ← 0.4,
Type ← -1,
Cj ← 1.92E-16,
Cjm ← 2.43E-16,
Pb ← 1.18
]
}; -- PETran
CTran: circuit[gate, source, drain |
L ← 2,
W ← 4, sdExtend ← 0, dWFact ← 1] = {
pt: PETran[gate, source, drain, Vdd |
l ← L,
w ← W,
as ← W*sdExtend,
ad ← W*sdExtend,
ps ← 2*sdExtend+(sdExtend>0)*W,
pd ← 2*sdExtend+(sdExtend>0)*W,
dWFact ← dWFact
]
NDTran: circuit[gate, source, drain |
-- from NMos4.0u75C.thy
L ← 4, W ← 2, sourceExtension ← 1, drainExtension ← 1, dWFact ← 1]= {
fet: MosFet[gate, source, drain, Gnd |
Lm ← L*Lambda,
Wm ← W*Lambda,
As ← sourceExtension*W*Lambda*Lambda,
Ad ← drainExtension*W*Lambda*Lambda,
Ps ← (2*sourceExtension+W)*Lambda,
Pd ← (2*drainExtension+W)*Lambda,
Vfb ← -4.23788,
Na ← 9.721774E+14,
Tox ← 700,
Lk1 ← -1.21598,
Wk1 ← 2.89924,
K20 ← -1.090938E-02,
Lk2 ← 9.20827,
Wk2 ← -0.935040,
Etao ← 2.529529E-02,
nEta ← 3.90803,
Un ← 636.284,
Vo ← 35.1750,
Lu ← -0.154980,
Ecrit ← 1.21462,
Lv ← 21.3101,
dL ← 0.550266,
dW ← -2.41600*dWFact,
TDegC ← Temp,
Cj ← 8.6E-17,
Cjm ← 2.17E-16,
Pb ← 0.9325
]
}; -- NDTran
WireCap: circuit[n |
-- l=length, w=width, a=area, p=perimeter
lM2 ← 0, wM2 ← 4, aM2 ← 0, pM2 ← 0, -- 2nd layer metal
lM ← 0, wM ← 3, aM ← 0, pM ← 0, -- 1rst layer metal
lP ← 0, wP ← 2, aP ← 0, pP ← 0, -- poly
aG← 0, pG ← 0, -- poly over thin oxide (if transistor unsimulated)
aM2C ← .197E-4pF, pM2C ← .486E-4pF, -- /(uM)^2, /uM, 2nd layer metal to bulk
aMC ← .276E-4pF, pMC ← .496E-4pF, -- 1rst layer metal to bulk
aPC ← .628E-4pF, pPC ← .577E-4pF, -- poly to bulk
aGC ← 11.8e-4pF -- poly over thin oxide
] = {
?: capacitor[n, Gnd] = Lambda*(Lambda*((aM2 + lM2*wM2)*aM2C + (aM + lM*wM)*aMC + (aP + lP*wP)*aPC + aG*aGC) + (pM2 + 2*lM2 + 2*wM2)*pM2C + (pM + 2*lM + 2*wM)*pMC + (pP + 2*lP)*pPC)
}; -- WireCap
DifCap: circuit[n |
lnD ← 0, wnD ← 0, anD ← 0, pnD ← 0, lpD ← 0, wpD ← 0, apD ← 0, ppD ← 0]= {
The 0-bias values are taken from ICL's "Report on Process and Electrical Parameters" by Richard Bruce and John Chen, dated 21 Feb 85. The n+ area and perimeter values in that report are measured, and the p+ area and perimeter values are inherited from I. Bol's MEC "Xerox CMOS Process Specification and Layout Design Rules" memo of February 83.
ndc: Diffusion[n, Gnd |
a ← (lnD*wnD+anD)*Lambda*Lambda,
p ← (2*(lnD+wnD)+pnD)*Lambda,
Cj ← 1.5E-4pF, -- /(um)^2
Cjm ← 3E-4pF, -- /um of sidewall
Pb ← 1.1265,
TDegC ← 100];
pdc: Diffusion[n, Gnd |
a ← (lpD*wpD + apD)*Lambda*Lambda,
p ← (2*(lpD + wpD) + ppD)*Lambda,
Cj ← 3.1E-4pF,
Cjm ← 3.0E-4pF,
Pb ← 1.18,
TDegC ← 100]
}; -- DifCap
WireRes: circuit[nodeA, nodeB |
lM2 ← 0, wM2 ← 4,
lM ← 0, wM ← 3,
lP ← 0, wP ← 2,
lnD ← 0, wnD ← 2,
lpD ← 0, wpD ← 2,
sM2R ← 0.06, -- ohms/square
sMR ← 0.06,
sPR ← 3.5, -- polysilicide
snDR ← 35,
spDR ← 120] = {
R: resistor[nodeA, nodeB] = lM2/wM2*sM2R + lM/wM*sMR + lP/wP*sPR + lnD/wnD*snDR + lpD/wpD*spDR
}; -- WireRes
ConRes: circuit[nodeA, nodeB |
nM2M ← 0, -- number of parallel 2nd layer metal to 1rst layer metal vias
nMP ← 0, -- number of parallel 1rst layer metal to poly contacts
nMD ← 0, -- number of parallel 1rst layer metal to diffusion contacts
nPD ← 0, -- number of parallel poly to diffusion contacts, butting
cM2MR ← 40, -- ohms/via, 2nd layer metal to 1rst layer
cMPR ← 4, -- ohms/contact, metal-polysilicide
cMDR ← 25, -- ohms/contact, metal-diffusion
cPDR ← 50 -- ohms/contact, poly-diffusion, with metal strap, i.e. butting contact
] = {
R: resistor[nodeA, nodeB] = 1/(nM2M/cM2MR + nMP/cMPR + nMD/cMDR + nPD/cPDR)
}; -- ConRes
Stray: circuit[n |
aM2 ← 0, pM2 ← 0,
aM ← 0, pM ← 0,
aP ← 0, pP ← 0,
anD ← 0, pnD ← 0,
apD ← 0, ppD ← 0,
aG ← 0, pG ← 0
] = {
wireCap: WireCap [n |
aM2 ← aM2, pM2 ← pM2,
aM ← aM, pM ← pM,
aP ← aP, pP ← pP,
aG ← aG, pG ← pG];
difCap: DifCap [n | anD ← anD, pnD ← pnD, apD ← apD, ppD ← ppD];
}; -- Stray
Change Log.
Created on June 11, 1983 5:51 PM. Entered parameters extracted by Akis Doganis for CMOS21, run 70, wafer 9, DIE=126-127. (cf. Akis' memo of May 17, 83.); Values for Cj, Cjm, and Pb were calculated from process data provided by RBruce. (SChen) Added parasitic circuits. (Barth)
McCreight, September 15, 1983 to add Stray capacitances from I. Bol's Xerox (ED) CMOS Spec of Feb 83
McCreight, October 18, 1983 5:27 PM to add simulated depletion NMOS
Ted Williams June 22, 1984 2:08 PM to add new extracted data from Akis Doganis for CSIM model. (CMOS36) Run 120, Wafer 10, DIE=128-127.
SChen, September 5, 1984 9:18:51 pm PDT, added new extracted data from Akis for CMOS-145 @100°C. Cf. Akis's memo of 30 Aug 84, 1984.
SChen, October 24, 1984 6:18:37 pm PDT, corrected calculations for Ps/Pd using sdExtension.
McCreight, March 5, 1985 3:02:34 pm PST
to cause calculated stray capacitances to agree with Wheeler's microstrip equations for fringing capacitance (Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane, IEEE Transactions on Microwave Theory and Techniques, vol MTT-25, No. 8, August, 1977, pp. 631-647).
to cause diffusion capacitances to agree with ICL's Report on Process and Electrical Parameters by R. Bruce and J. Chen, 21 Feb 85.