
<<File: BSim.thy>>
<<Last Edited by:>>
    <<Sweetsun Chen, July 19, 1985 4:57:27 pm PDT>>
<<McCreight, April 16, 1985 10:34:08 am PST>>

BSimMOS: CIRCUIT [gate, source, drain, bulk | L _ 2, W _ 20, Cox _ 11.8E-4pF --/um^2--, type _ 2, dutZratio _ 0 ] =
{
bsimModel: model _ BSimFromFile[gate, source, drain, bulk |
<<BSIM extraction, lot 205, wafer 5, device (125,127), 26 Mar 85 by Oki >>
L, -- Length (microns), later VFB (volts)
W, -- Width (microns), later twoPhiF (volts)
dutZratio, -- dutZRatio (W/L, 0 defaults to W/L ratio in file), later k1 (volts^0.5)
0, -- k2 ()
0, -- eta ()
0, -- beta0 (farads/(volt*second))
0, -- u0 (1/volts)
0, -- u1 (1/volts)
0, -- x2beta0
0, -- x2eta
0, -- x3eta
0, -- x2u0
0, -- x2u1
0, -- beta0sat
0, -- x2beta0sat
0, -- x2beta0sat
0, -- x3u1
0, -- n0 ... I don't know in what order these last three go...
0, -- x2nb
0, -- x3nd

0, -- vdd (volts)
273.15+TDegC, -- temp (Kelvins)

Cox*L*W, -- MCgbo (farads) (?)
Cox*L*W*2.0/3.0, -- Cgbo23rds (farads)
0, -- maxFwdBias (Vbs excess over twoPhiF) (volts)
0, -- noCap (0 => compute capacitances, 1 => don't)
type -- type (>0 => nChannel, <0 => pChannel, ABS[type]>1 selects process file "BSIMProcess-n.process")
];

i: current[drain, source] _ bsimModel[0];
cgb: capacitor[gate, bulk] _ bsimModel[1];
cgs: capacitor[gate, source] _ bsimModel[2];
cgd: capacitor[gate, drain] _ bsimModel[3];
}; -- BSimMOS

BasicDifCap: CIRCUIT [cathode, anode |
Co _ 0 -- farads --,
PhiZero _ 0.9 -- junction built-in potential, volts --,
Vt _ .026 -- kT/q, volts --,
Io _ -5pA -- reverse current, amps --,
VMax _ 0.6 -- volts --] =
{
sdCapModel: model _ SDDiode[cathode, anode |
Co,
1/PhiZero,
1/Vt,
Io,
VMax];
?: capacitor[cathode, anode] _ sdCapModel[0];
?: current[cathode, anode] _ sdCapModel[1];
};

NMOSDifCap: CIRCUIT [dif, bulk | perim _ 0 --um--, area _ 0 --um^2-- ] =
{
?:BasicDifCap[dif, bulk |
Co _ 1.5E-4pF*area,
PhiZero _ 0.90, --?--
Vt _ 1/(8.617E-5*(TDegC+273.16)),
Io _ -5pA*area
];
?:BasicDifCap[dif, bulk |
Co _ 3.0E-4pF*perim,
PhiZero _ 0.90, --?--
Vt _ 1/(8.617E-5*(TDegC+273.16)),
Io _ -5pA*perim
];
};

PMOSDifCap: CIRCUIT [dif, bulk | perim _ 0 --um--, area _ 0 --um^2-- ] =
{
?:BasicDifCap[bulk, dif |
Co _ 3.1E-4pF*area,
PhiZero _ 0.94, --?--
Vt _ 1/(8.617E-5*(TDegC+273.16)),
Io _ -5pA*area
];
?:BasicDifCap[bulk, dif |
Co _ 3.0E-4pF*perim,
PhiZero _ 0.94, --?--
Vt _ 1/(8.617E-5*(TDegC+273.16)),
Io _ -5pA*perim
];
};

ETran: CIRCUIT [gate, source, drain | L _ 2, W _ 4, sdExtend _ 0, dWFact _ 1, type _ 2, dutZratio _ 0] = {
nt: BSimMOS[gate, source, drain, Gnd | L _ L, W _ W, type _ type, dutZratio _ dutZratio];
dCap: NMOSDifCap[drain, Gnd |
perim _ (sdExtend#0)*(2*sdExtend+W), area _ sdExtend*W ];
sCap: NMOSDifCap[source, Gnd |
perim _ (sdExtend#0)*(2*sdExtend+W), area _ sdExtend*W];
}; -- ETran


CTran: CIRCUIT [gate, source, drain | L _ 2, W _ 4, sdExtend _ 0, dWFact _ 1, type _ -3, dutZratio _ 0] = {
pt: BSimMOS[gate, source, drain, Vdd | L _ L, W _ W, type _ type, dutZratio _ dutZratio];
dCap: PMOSDifCap[drain, Vdd |
perim _ (sdExtend#0)*(2*sdExtend+W), area _ sdExtend*W ];
sCap: PMOSDifCap[source, Vdd |
perim _ (sdExtend#0)*(2*sdExtend+W), area _ sdExtend*W];
}; -- CTran

WireCap:  circuit[n | -- l=length, w=width, a=area, p=perimeter
lM2 _ 0, wM2 _ 4, aM2 _ 0, pM2 _ 0, -- 2nd layer metal
lM _ 0, wM _ 3, aM _ 0, pM _ 0,  -- 1rst layer metal
lP _ 0, wP _ 2, aP _ 0, pP _ 0,  -- poly
aG_ 0, pG _ 0, -- poly over thin oxide (if transistor unsimulated)
aM2C _ .197E-4pF, pM2C _ .486E-4pF, -- /(uM)^2, /uM, 2nd layer metal to bulk
aMC _ .276E-4pF, pMC _ .496E-4pF,  -- 1rst layer metal to bulk
aPC _ .628E-4pF, pPC _ .577E-4pF,  -- poly to bulk
aGC _ 11.8e-4pF -- poly over thin oxide
] = {

C: capacitor[n, Gnd] = Lambda*(Lambda*((aM2 + lM2*wM2)*aM2C + (aM + lM*wM)*aMC + (aP + lP*wP)*aPC + aG*aGC) + (pM2 + 2*lM2 + 
2*wM2)*pM2C + (pM + 2*lM + 2*wM)*pMC + (pP + 2*lP)*pPC)
}; -- WireCap

Stray:  circuit[n |
aM2 _ 0, pM2 _ 0,
aM _ 0, pM _ 0,
aP _ 0, pP _ 0,
anD _ 0, pnD _ 0,
apD _ 0, ppD _ 0,
aG _ 0, pG _ 0
] = {

wireCap: WireCap [n |
aM2 _ aM2, pM2 _ pM2,
aM _ aM, pM _ pM,
aP _ aP, pP _ pP,
aG _ aG, pG _ pG];

nCap: NMOSDifCap [n, Gnd | area _ Lambda*Lambda*anD, perim _ Lambda*pnD];
pCap: PMOSDifCap [n, Vdd | area _ Lambda*Lambda*apD, perim _ Lambda*ppD];
}; -- Stray