Cabbage:
CEDAR
DEFINITIONS =
BEGIN
Theory
This interface allows easy routing of interior of chips to pad frames. Interconnection requirements are specified by the Connections interface. The input objects are the interior of the chip, the four sides of the chip containing the pads, and the four corners of the pad frame. Signal connections to the corners are not allowed.
Routing is performed in two modes: normal and pad limited.
Normal routing is performed in eight areas: four channels whose length are defined by the dimensions of the interior object, and four switchboxes in the corners. Pins on the bonding pad sides are not allowed to cross the "seams" among the routing areas.
Pad limited routing is performed in four areas: two channels whose length are defined by the dimensions of the interior object, and two switchboxes on the upper and lower surfaces. Pins on the bonding pad sides are not allowed to cross the "seams" among the routing areas.
Nets with the names "Vdd" and "Gnd" are distinguished. The are not permitted to participate in constraint loops with each other. Pins of these nets on the side surfaces the conflict with pins of the other net are not included in the routing.
Restrictions:
1. Currently, it is a client requirement to place the interior object so that projections of its edges do not intersect pins on the bonding pad sides. This will be relaxed in future versions.
2. Currently wire widths specifications from Connections are transformed to net names. This means that there can be only one wire width per net name. This will be relaxed when Connections is moved into Route.
3. Incomplete routing may occur if the switchbox areas (the corners) are too small or too congested in a part of the switchbox. Automatic recovery is planned but not implemented.
4. The portions of the left and right bonding pad sides that are routed with switchboxes can have only one net per portion. Also, these portions must have "sparse" connections: spacing should be much greater than the minimum pin-to-pin spacing .
Errors
Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
Signal: SIGNAL [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
ErrorType: TYPE = {programmingError, callingError, noResource, designRuleViolation, other};
Common Types
ROPE: TYPE = Rope.ROPE;
Side: TYPE ~ Route.Side;
Object: TYPE = CD.Object;
Types
-- All the parameters for the channel and switchbox router
PadRingParams: TYPE = REF PadRingParamsRec;
PadRingParamsRec:
TYPE =
RECORD [
horizLayer: ROPE, -- "poly", "metal" or "metal2"
vertLayer: ROPE, -- "poly", "metal" or "metal2"
technologyKey: ATOM ← $cmosB, -- $cmosA or $cmosB
wireWidthProc: PWRoute.WireWidthProc ← NIL, -- to control the width of a trunk wire
outerChanWidth: INT ← 256, -- width of channel at periphery in CnD units
powerCellWidth : INT ← 1700, -- width of channel at periphery in CnD units
opt: Route.Optimization ← full, -- controls runtime vs quality
signalIncomplete: BOOLEAN ← TRUE, -- SIGNAL if there are any incompletes
signalSinglePinNets: BOOLEAN ← TRUE, -- SIGNAL if there are any single pin nets
viaTable: HashTable.Table ← NIL -- hash table for testing contact definitions
];
The pad router will signal if design rule violations are found in the input. Proceeding from the signals may cause design rule violations in the routing!! Setting the Signal Booleans to FALSE should be used with caution!!
defaultPadRingParams: PadRingParams;
Function
Returns the innerPos needed for centering the inner in the pad frame. This is usually what is desired. However the position of the inner cell can be positioned other than in the center. Refer to discussion of PadRoute.
Center:
PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: Object, parms: Cabbage.PadRingParams]
RETURNS [innerPos:
CD.Position];
Extends the wires of oldInner to make an proper inner. The extension takes into account the routing layer. Not yet implemented.
MakeInner:
PROC [oldInner: Object, connections: Connections.Table, parms: PadRingParams]
RETURNS [inner: Object];
Extends the wires of oldPadSides to make an proper PadSides. The extension takes into account the routing layer. Not yet implemented.
MakeOuter:
PROC [oldOuter: Object, side: Side, connections: Connections.Table, parms: PadRingParams]
RETURNS [outer: Object];
Route the chip:
Two procedured are supplied: PadRoute and PadLimitedRoute. PadRoute will work for all chips but sometimes does not exploit the area in the corners of pad limited chips well. PadLimitedRoute divides the routing areas differently to route pad limited chips better.
inner is the interior part of the chip
bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left are the objects in the pad ring; any may be NIL. Dimensions of the corner objects should not be smaller than the projections of their adjacent sides. The pad ring objects are "glued" together with wiring for those connections that are compatabel at the boundries.
innerPos must place the inner object in the interior of the padring; otherwise it is ignored. The origin of the coordinate system is the lower left corner of the assemblrd pad ring.
connections specifies those points to be connected
parms specifies the physical parameters and the runtime options
if name is specified, the chip is created with that name
Note: This version requires that the inner object be positioned so that the "seams" between the routing areas (the projections of the edges of the inner object through the routing area) must not intersect a pin on the pad ring. Future versions will relax this restriction.
PadRoute:
PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: Object, innerPos:
CD.Position, connections: Connections.Table, parms: PadRingParams ← defaultPadRingParams, name: Rope.
ROPE ←
NIL]
RETURNS [chip: Object];
PadLimitedRoute: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: Object, innerPos: CD.Position, connections: Connections.Table, parms: PadRingParams ← defaultPadRingParams, name: Rope.ROPE ← NIL] RETURNS [chip: Object];
END.