DIRECTORY Core, CoreClasses, CoreFlat, HashTable, IO, LinearSystem, PlotGraph, Rope, Schedule; Mint: CEDAR DEFINITIONS ~ BEGIN ps: TYPE = REAL; -- picosecond (1e-12 s) mVolt: TYPE = REAL; -- millivolt (1e-3 V) pF: TYPE = REAL; -- picofarad (1e-12 F) ohm: TYPE = REAL; -- W Circuit: TYPE = REF CircuitRec; -- global handle CircuitRec: TYPE = RECORD [ rootCell: Core.CellType, nodeTable: HashTable.Table, agenda: Schedule.Agenda _ NIL, library: Library _ NIL, fetTypeList: LIST OF FetType, info: Info, private: MintPrivateData ]; Info: TYPE = REF InfoRec; InfoRec: TYPE = RECORD [ totalNodes: INT _ 0, eachWireCapa: pF _ 0.0, totalFets: ARRAY CoreClasses.TransistorType OF INT _ ALL[0], nbOfSimulations: INT _ 0, tStart: ps _ 0.0, tStop: ps _ 1.0e5 ]; MintPrivateData: PUBLIC TYPE = REF MintPrivateDataRec; MintPrivateDataRec: TYPE = RECORD[ matrix: LinearSystem.MatrixN, cstTerm: LinearSystem.ColumnN, vInit: LinearSystem.ColumnN, tau: LinearSystem.ColumnN, copyMatrix: LinearSystem.MatrixN, subMatrix: LinearSystem.MatrixN, fetSeqPool: ARRAY [1..128] OF LIST OF FetSeq _ ALL[NIL] ]; NodeList: TYPE = LIST OF Node; NodeSeq: TYPE = REF NodeSeqRec; NodeSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Node]; Node: TYPE = REF NodeRec; -- others call them wires NodeRec: TYPE = RECORD [ flatWire: CoreFlat.FlatWire, history: Schedule.History, --Last notables events around cap: REAL, --Intrinsic capacitance. fetSeq: FetSeq, --fets connnecting to this node. setList: SetList, --sets connnecting their inputs to this node. input, --node forced to a fixed value by outside world. watched, --means the value of the node is used by the outside world fixedV, --this node is a power node done: BOOLEAN _ FALSE, ignoreMe: BOOLEAN _ FALSE, index: CARDINAL ]; FetList: TYPE = LIST OF Fet; FetSeq: TYPE = REF FetSeqRec; FetSeqRec: TYPE = RECORD [nUsed: NAT _ 0, elements: SEQUENCE size: NAT OF Fet]; Fet: TYPE = REF FetRec; FetRec: TYPE = RECORD [ gate, ch1, ch2: Node, --Nodes connecting to transistor. type: FetType, --Type of transistor switch, --TRUE means that the fet is turn on done: BOOLEAN _ FALSE --multi purpose flag ]; FetType: TYPE = REF FetTypeRec; FetTypeRec: TYPE = RECORD [ l: NAT, -- transistor length w: NAT, -- transistor width type: CoreClasses.TransistorType, rOnInv: REAL -- Inverse of equivalent resistance when the fet is on ]; SetList: TYPE = LIST OF Set; SetSeq: TYPE = REF SetSeqRec; SetSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Set]; Set: TYPE = REF SetRec; --two fets are in the same set iff there is a path between them SetRec: TYPE = RECORD [ --following sources and drains lFets: FetList _ NIL, lNodes: NodeList _ NIL, --nodes connecting the fets of the set inList: NodeList _ NIL, --other nodes connected to the gates of the fets (set inputs) fixedV: NodeList _ NIL, --nodes fixed by the outside world (like Vdd and Gnd) type: SetType _ NIL, done: BOOLEAN _ FALSE --multi purpose flag ]; SetType: TYPE = REF SetTypeRec; -- some figures allowing easy recognition of simple structures SetTypeRec: TYPE = RECORD [ nFets: ARRAY CoreClasses.TransistorType OF CARDINAL _ ALL[0], nVddTran, nGndTran, nNodes, nInput: CARDINAL _ 0, solve: SolveProc _ NIL ]; SolveProc: TYPE = PROC[set: Set, t: ps, circuit: Circuit] RETURNS [nextTime: ps]; Caminos: TYPE = LIST OF Camino; Camino: TYPE = RECORD[length: REAL, data: LIST OF CaminoCell]; CaminoCell: TYPE = RECORD[set: Set, node: Node]; Library: TYPE = LIST OF LibraryElem _ NIL; -- the sets accessed by SetType. LibraryElem: TYPE = REF LibraryElemRec; LibraryElemRec: TYPE = RECORD [ type: SetType, nElem: CARDINAL _ 0, setList: SetList _ NIL ]; TypeTable: ARRAY CoreClasses.TransistorType OF TType; -- for physical constants TType: TYPE = REF TTypeRec; TTypeRec: TYPE = RECORD [ name: Rope.ROPE, cPerArea, cPerWidth: REAL, rOn: REAL ]; StdOut: IO.STREAM; ignoreMe: ATOM; -- $MintIgnoreMe. This prop stops the analysis of a path for timing if set to $TRUE. Could be on a celltype, instance or wire. CircuitSimulate: PROC[circuit: Circuit, from: ps _ 0.0] RETURNS [t: ps]; InteractiveSimulate: PROC [circuit: Circuit, watchList: NodeList _ NIL, from: ps _ 0.0]; PrintFet: PROC [fet: Fet, circuit: Circuit]; PrintNode: PROC [node: Node, circuit: Circuit]; PrintFetList: PROC [fetList: FetList, circuit: Circuit]; PrintNodeList: PROC [nodeList: NodeList, circuit: Circuit]; PrintCamino: PROC [camino: Camino, circuit: Circuit]; PrintCaminos: PROC [caminos: Caminos, circuit: Circuit]; EditNodeHistory: PROC [node: Node, t: ps, v: mVolt]; EditNodeInputBool: PROC [node: Node, forcedInput: BOOLEAN]; NodeFromRope: PROC [id: Rope.ROPE, circuit: Circuit] RETURNS [node: Node]; RopeFromNode: PROC [node: Node, circuit: Circuit] RETURNS [id: Rope.ROPE]; SetNode: PROC [node: Node, val, input: BOOLEAN _ TRUE, t: ps _ 0.0]; GetNode: PROC [node: Node] RETURNS [val: BOOLEAN]; SettledValuesOfNode: PROC [node: Node] RETURNS [t: ps, v: mVolt]; KillFetList: PROC [fetList: FetList]; KillNodeList: PROC [nodeList: NodeList]; KillSetList: PROC [setList: SetList, killSets: BOOLEAN _ TRUE]; KillCircuit: PROC [circuit: Circuit]; MaxFreqEvaluate: PROC [circuit: Circuit, clkList: NodeList, numberOfPaths: CARD, from: ps _ 0.0, histOk: BOOLEAN _ TRUE] RETURNS [worst: ps _ 0.0, caminos: Caminos]; MaxCapa: PROC [circuit: Circuit, n: NAT _ 1] RETURNS [fatest: REAL, fatNodes: NodeList]; LastTime: PROC [circuit: Circuit, n: NAT _ 1] RETURNS [veryLastTime: ps, slowNodes: NodeList]; SetTime: PROC [t: ps, circuit: Circuit]; DrawNodeList: PROC [nodeList: NodeList, circuit: Circuit] RETURNS[plot: PlotGraph.Plot]; AddNodeToPlot: PROC [node: Node, plot: PlotGraph.Plot, r: Rope.ROPE _ NIL]; CreateCircuit: PROC [rootCell: Core.CellType] RETURNS [circuit: Circuit]; InputData: PROC [circuit: Circuit, fixedVList: NodeList, layout: BOOLEAN _ TRUE, eachWireCapa: pF _ 0.0]; CreatePrivate: PUBLIC PROC [circuit: Circuit]; PrepareSets: PROC [circuit: Circuit, fixedVList: NodeList]; CheckLibrary: PROC [circuit: Circuit]; OutputResults: PROC [circuit: Circuit]; END. ΈMint.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Christian LeCocq April 17, 1987 5:36:18 pm PDT UNITS MintPrivateData: TYPE = REF; -- caches of matrices and so on... Build the initial calendar of events and simulate until a steady state is reached. the same as CircuitSimulate except that it builds and refreshes a display. Prints the type, size, switch and ports of the fet. Prints the name and list of HistoryPts on StdOut The basic way to specify the stimuli. The events must be edited in time order, a modification of the middle of the history deletes the end of the history from this time. Specifies the fact that a node is or is not a voltage source. Vdd and Gnd are inputs. Finds the node with the specified (ROPE) name. gives the rope name of the node. edits the value of the node for t. gives the last value of the node gives the last value of the node 4 procs to improve GC use. If killSets then KillSetList will kill the LIST and each set of the List, else it will kill only the LIST; finds the numberOfPaths longest paths in the circuit. if histOk then a Histogram of the path through time is created. computes and print the laziest nodes. Print on StdOut the tup and tdown of the n slowest ones. gives you the n last nodes to settle for the circuit. Cuts all histories at t. Builds the oscilloscope that display this list of Nodes. Appends a graph showing node to plot, using r as a name if specified. create the empty data structure with only the top level public, so that you can specify the power nodes before actually constructing the "Circuit" with InputData. Builds the handle of Mint data from the Core structures. Cuts the Mint flat circuit into sets and store them by type in the circuit library. Called by InputData. Verify the static connectivity: isolated nodes, nodes that cannot be driven, node not reachable from Vdd or Gnd. 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