DIRECTORY Core, CoreClasses, CoreFlat, HashTable, IO, Names, PlotGraph, Rope, Schedule; Mint: CEDAR DEFINITIONS ~ BEGIN ps: TYPE = REAL; -- picosecond (1e-12 s) mVolt: TYPE = REAL; -- millivolt (1e-3 V) pF: TYPE = REAL; -- picofarad (1e-12 F) ohm: TYPE = REAL; -- W Circuit: TYPE = REF CircuitRec; -- global handle CircuitRec: TYPE = RECORD [ rootCell: Core.CellType, nodeTable: HashTable.Table, agenda: Schedule.Agenda _ NIL, library: Library _ NIL, info: Info ]; Info: TYPE = REF InfoRec; InfoRec: TYPE = RECORD [ totalNodes: INT _ 0, capNodes: INT _ 0, totalFets: ARRAY TranType OF INT _ ALL[0], nbOfSimulations: INT _ 0 ]; TranType: TYPE = CoreClasses.TransistorType; Node: TYPE = REF NodeRec; -- others call them wires NodeRec: TYPE = RECORD [ flatWire: CoreFlat.FlatWire, history: Schedule.History, --Last notables events around cap: REAL, --Intrinsic capacitance. fetList: FetList, --list of fets connnecting to this node. setList: SetList, --list of sets connnecting their inputs to this node. input, --node forced to a fixed value by outside world. watched, --means the value of the node is used by the outside world done: BOOLEAN _ FALSE, index: CARDINAL ]; Fet: TYPE = REF FetRec; FetRec: TYPE = RECORD [ gate, ch1, ch2: Node, --Nodes connecting to transistor. rOnInv: REAL, --Inverse of equivalent resistance when the fet is on type: CoreClasses.TransistorType, --Type of transistor switch, --TRUE means that the fet is turn on done: BOOLEAN _ FALSE --multi purpose flag ]; Set: TYPE = REF SetRec; --two fets are in the same set iff there is a path between them SetRec: TYPE = RECORD [ --following sources and drains lFets: FetList _ NIL, lNodes: NodeList _ NIL, --nodes connecting the fets of the set inList: NodeList _ NIL, --other nodes connected to the gates of the fets (set inputs) fixedV: NodeList _ NIL, --nodes fixed by the outside world (like Vdd and Gnd) type: SetType _ NIL, done: BOOLEAN _ FALSE --multi purpose flag ]; SetType: TYPE = REF SetTypeRec; -- some figures allowing easy recognition of simple structures SetTypeRec: TYPE = RECORD [ nFets: ARRAY CoreClasses.TransistorType OF CARDINAL _ ALL[0], nVddTran, nGndTran, nNodes, nInput: CARDINAL _ 0, solve: SolveProc _ NIL ]; SolveProc: TYPE = PROC[set: Set, t: ps, circuit: Circuit] RETURNS [nextTime: ps]; NodeList: TYPE = LIST OF Node; FetList: TYPE = LIST OF Fet; SetList: TYPE = LIST OF Set; Library: TYPE = LIST OF LibraryElem _ NIL; -- the sets accessed by SetType. LibraryElem: TYPE = REF LibraryElemRec; LibraryElemRec: TYPE = RECORD [ type: SetType, nElem: CARDINAL _ 0, setList: SetList _ NIL ]; TypeTable: ARRAY CoreClasses.TransistorType OF TType; -- for physical constants TType: TYPE = REF TTypeRec; TTypeRec: TYPE = RECORD [ name: Rope.ROPE, rOn: REAL ]; StdOut: IO.STREAM; CircuitSimulate: PROC[circuit: Circuit, from: ps _ 0.0] RETURNS [t: ps]; PrintFet: PROC [fet: Fet, circuit: Circuit]; PrintNode: PROC [node: Node, circuit: Circuit]; PrintFetList: PROC [fetList: FetList, circuit: Circuit]; PrintNodeList: PUBLIC PROC [nodeList: NodeList, circuit: Circuit]; EditNodeHistory: PROC [node: Node, t: ps, v: mVolt]; EditNodeInputBool: PROC [node: Node, forcedInput: BOOLEAN]; NodeFromRope: PUBLIC PROC [id: Rope.ROPE, circuit: Circuit] RETURNS [node: Node]; RopeFromNode: PUBLIC PROC [node: Node, circuit: Circuit] RETURNS [id: Rope.ROPE]; SetNode: PROC [node: Node, val, input: BOOLEAN _ TRUE, t: ps _ 0.0]; GetNode: PROC [node: Node] RETURNS [val: BOOLEAN]; SettledValuesOfNode: PROC [node: Node] RETURNS [t: ps, v: mVolt]; KillFetList: PUBLIC PROC [fetList: FetList]; KillNodeList: PUBLIC PROC [nodeList: NodeList]; KillSetList: PUBLIC PROC [setList: SetList, killSets: BOOLEAN _ TRUE]; KillCircuit: PUBLIC PROC [circuit: Circuit]; MaxFreqEvaluate: PROC [circuit: Circuit, clkList: NodeList, from: ps _ 0.0] RETURNS [worst: ps _ 0.0, setList: SetList]; MaxCapa: PUBLIC PROC [circuit: Circuit, n: NAT _ 1] RETURNS [fatest: REAL, fatNodes: NodeList]; LastTime: PROC [circuit: Circuit, n: NAT _ 1] RETURNS [veryLastTime: ps, slowNodes: NodeList]; Watch: PROC [watchList: NodeList]; SetTime: PROC [t: ps, circuit: Circuit]; DrawNodeList: PROC [nodeList: NodeList, circuit: Circuit] RETURNS[plot: PlotGraph.Plot]; AddNodeToPlot: PUBLIC PROC [node: Node, plot: PlotGraph.Plot, r: Rope.ROPE _ NIL]; InputData: PROC [ct: Core.CellType, layout: BOOLEAN _ TRUE] RETURNS [circuit: Circuit]; BuildNodeList: PROC [name: Rope.ROPE, oldList: NodeList, circuit: Circuit] RETURNS [newList: NodeList]; PrepareSets: PROC [circuit: Circuit, fixedVList: NodeList]; CheckLibrary: PROC [circuit: Circuit]; OutputResults: PROC [circuit: Circuit]; END. �����Mint.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Christian LeCocq December 15, 1986 10:09:33 am PST UNITS cPerArea, cPerWidth: REAL, -- now part of WriteCapa Build the initial calendar of events and simulate until a steady state is reached. Prints the type, size, switch and ports of the fet. Prints the name and list of HistoryPts on StdOut The basic way to specify the stimuli. The events must be edited in time order, a modification of the middle of the history deletes the end of the history from this time. Specifies the fact that a node is or is not a voltage source. Vdd and Gnd are inputs. Finds the node with the specified (ROPE) name. gives the rope name of the node. edits the value of the node for t. gives the last value of the node gives the last value of the node 4 procs to improve GC use. If killSets then KillSetList will kill the LIST and each set of the List, else it will kill only the LIST; finds the longest path in the circuit. May be... computes and print the laziest nodes. Print on StdOut the tup and tdown of the n slowest ones. gives you the n last nodes to settle for the circuit. The watched nodes never forget, but their history management is slow. Cuts all histories at t. Builds the oscilloscope that display this list of Nodes. Appends a graph showing node to plot, using r as a name if specified. Builds the handle of Mint data from the Core structures. Adds a Node to a list of Nodes from its name, without creating a new Node if the Node is not found in the circuit. Cuts the Mint flat circuit into sets and store them by type in the circuit library. Verify the static connectivity: isolated nodes, nodes that cannot be driven, node not reachable from Vdd or Gnd. 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