DIRECTORY
CD USING [ Design, Instance, InstanceList],
CDMenus USING [CreateEntry],
CDOps USING [InstList],
CDProperties USING [PutDesignProp],
CDSequencer USING [Command, ImplementCommand],
Core USING [CellType],
IO USING [PutF, real],
Mint,
Rope USING [ROPE],
Sisyph USING [mode],
Sinix USING [Mode],
SinixOps,
TerminalIO USING [WriteRope],
WriteCapa;
CDMint: CEDAR PROGRAM
IMPORTS 
CDMenus, CDOps, CDProperties, CDSequencer, IO, Mint, Sisyph, SinixOps, TerminalIO, WriteCapa
~ BEGIN
debugCircuit: Mint.Circuit;
verbose: BOOLEAN _ FALSE;
maxNumber: NAT _ 10;

ExtractAndPrepare: PROC [mode: Sinix.Mode, comm: CDSequencer.Command] RETURNS[circuit: Mint.Circuit, instance: CD.Instance] ~ {
IF mode=NIL THEN {
TerminalIO.WriteRope ["technology unknown.\n"];
RETURN
};
FOR all: CD.InstanceList _ CDOps.InstList [comm.design], all.rest WHILE all # NIL DO
IF all.first.selected THEN {
fixedV: Mint.NodeList;
coreCell: Core.CellType;
isLayout: BOOLEAN _ mode#Sisyph.mode;
instance _ all.first;
coreCell _ NARROW[SinixOps.ExtractCDInstance [instance, comm.design, mode].result];
WriteCapa.WriteWireCapa[coreCell, comm.design.technology.key];
circuit _ Mint.InputData[coreCell, isLayout];
fixedV _ Mint.BuildNodeList["public.Vdd", NIL, circuit];
Mint.SetNode[fixedV.first, TRUE];
fixedV _ Mint.BuildNodeList["public.Gnd", fixedV, circuit];
Mint.SetNode[fixedV.first, FALSE];
Mint.PrepareSets[circuit, fixedV];
RETURN;
};
ENDLOOP
};

ShowSetList: PROC [decoration: SinixOps.Decoration, design: CD.Design, instance: CD.Instance, root: Core.CellType, setList: Mint.SetList] ~ {
flatWires: LIST OF SinixOps.FlatWireRec _ NIL;
FOR inode: Mint.NodeList _ setList.first.lNodes, inode.rest UNTIL inode=NIL DO
flatWires _ CONS[inode.first.flatWire^, flatWires];
ENDLOOP;
FOR iSetList: Mint.SetList _ setList, iSetList.rest UNTIL iSetList.rest=NIL DO
set1: Mint.Set _ iSetList.first;
set2: Mint.Set _ iSetList.rest.first;
FOR inode: Mint.NodeList _ set1.inList, inode.rest UNTIL inode=NIL DO
found: BOOLEAN _ FALSE;
FOR inode2: Mint.NodeList _ set2.lNodes, inode2.rest UNTIL inode2=NIL DO
IF inode2.first=inode.first THEN {found _ TRUE; EXIT};
ENDLOOP;
IF found THEN flatWires _ CONS[inode.first.flatWire^, flatWires];
ENDLOOP;
ENDLOOP;
SinixOps.HighlightNets[decoration, design, instance, root, flatWires];
};

ExtractAndTiming: PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
worst: Mint.ps;
setList: Mint.SetList;
circuit: Mint.Circuit;
clkList: Mint.NodeList;
instance: CD.Instance;
[circuit, instance] _ ExtractAndPrepare[mode, comm];
clkList _ LIST[ Mint.NodeFromRope[clkName, circuit]];
[worst, setList] _ Mint.MaxFreqEvaluate[circuit, clkList, 0.0];
IO.PutF[Mint.StdOut, "longest time: %4.1f\n", IO.real[worst]];
ShowSetList[mode.decoration, comm.design, instance, circuit.rootCell, setList];
Mint.KillCircuit[circuit];
};

ExtractAndCheck: PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
circuit: Mint.Circuit _ ExtractAndPrepare[mode, comm].circuit;
Mint.CheckLibrary[circuit];
debugCircuit _ circuit;
};


TimingFromLayout: PROC [comm: CDSequencer.Command] ~ {
abort: REF BOOL _ NEW [BOOL_FALSE];
mode: Sinix.Mode _ SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["TimingLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndTiming[mode, comm];
TerminalIO.WriteRope ["Timing finished.\n"];
};

TimingFromSchematics: PROC [comm: CDSequencer.Command] ~ {
abort: REF BOOL _ NEW [BOOL_FALSE];
TerminalIO.WriteRope ["TimingSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndTiming[Sisyph.mode, comm];
TerminalIO.WriteRope ["Timing finished.\n"];
};

CheckFromLayout: PROC [comm: CDSequencer.Command] ~ {
abort: REF BOOL _ NEW [BOOL_FALSE];
mode: Sinix.Mode _ SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["CheckLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndCheck[mode, comm];
TerminalIO.WriteRope ["Check finished.\n"];
};

CheckFromSchematics: PROC [comm: CDSequencer.Command] ~ {
abort: REF BOOL _ NEW [BOOL_FALSE];
TerminalIO.WriteRope ["CheckSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndCheck[Sisyph.mode, comm];
TerminalIO.WriteRope ["Check finished.\n"];
};


clkName: Rope.ROPE _ "public.CK";
CDSequencer.ImplementCommand [key: $CheckLayoutSel, proc: CheckFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Check", key: $CheckLayoutSel];
CDSequencer.ImplementCommand [key: $CheckSchemSel, proc: CheckFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Check", key: $CheckSchemSel];
CDSequencer.ImplementCommand [key: $TimingLayoutSel, proc: TimingFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Timing", key: $TimingLayoutSel];
CDSequencer.ImplementCommand [key: $TimingSchemSel, proc: TimingFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Timing", key: $TimingSchemSel];
TerminalIO.WriteRope ["CDMint package loaded.\n"];
END.
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Copyright (C) 1985 by Xerox Corporation.  All rights reserved.
Christian LeCocq January 15, 1987 10:43:32 am PST
Mike Spreitzer November 18, 1986 6:21:02 pm PST

Bridge beetween ChipNDale, Core and Mint.
IF isLayout THEN WriteCapa.WriteWireCapa[coreCell, comm.design.technology.key];
fixedV _ Mint.BuildNodeList["PadVdd", fixedV, circuit]; -- if there is no PadAlims,
Mint.SetNode[fixedV.first, TRUE];
fixedV _ Mint.BuildNodeList["PadGnd", fixedV, circuit]; -- they will be ignored.
Mint.SetNode[fixedV.first, FALSE];
ExtractAndMint: PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
circuit: Mint.Circuit _ ExtractAndPrepare[mode, comm].circuit;
IF verbose THEN Mint.OutputResults[circuit];
[] _ Mint.MaxCapa[circuit, maxNumber];
debugCircuit _ circuit;
};
Called by ChipNDale upon activation of the command.
Called by ChipNDale upon activation of the command.
Called by ChipNDale upon activation of the command.
Called by ChipNDale upon activation of the command.
MintFromLayout: PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL _ NEW [BOOL_FALSE];
mode: Sinix.Mode _ SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["MintLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndMint[mode, comm];
TerminalIO.WriteRope ["Mint input finished.\n"];
};

MintFromSchematics: PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL _ NEW [BOOL_FALSE];
TerminalIO.WriteRope ["MintSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndMint[Sisyph.mode, comm];
TerminalIO.WriteRope ["Mint input finished.\n"];
};
CDSequencer.ImplementCommand [key: $MintLayoutSel, proc: MintFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Mint", key: $MintLayoutSel];
CDSequencer.ImplementCommand [key: $MintSchemSel, proc: MintFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Mint", key: $MintSchemSel];
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