MintDoc.tioga
Copyright © 1986 by Xerox Corporation. All rights reserved.
Written by: Christian LeCocq August 5, 1986 11:20:25 am PDT
MINT: MINIMUM TIME SIMULATOR
MINT: MINIMUM TIME SIMULATOR
MINT: MINIMUM TIME SIMULATOR
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
Mint: MINimum Time simulator
Christian Le Cocq
User Manual
Release as [DATools]<DATools6.1>Mint>MintDoc.tioga, .press
© Copyright 1986 Xerox Corporation. All rights reserved.
Abstract: Mint is a program that simulates a Core data structure extracted from a layout.
Created by: Christian Le Cocq
Maintained by: Le Cocq <LeCocq.pa>
Keywords: Circuit Simulation, Graph Display
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
Introduction
The Purpose of Mint is to provide a fast verification of logic and timing features of a piece of layout. Mint is faster and less accurate than Thyme and can handle many more fets in a reasonable amount of time. Its time evaluations are more reliable than Crystal ones, as it takes into account the logical states of the circuit inner.
Programming Interface
The simulation interface resides in Mint.mesa, and the display and print interfaces in MintDisplay.mesa.
User Interface
The user interface for Mint consists of one command called "SINIX -> Mint", available via the <space>-P menu of ChipNDale. This command takes a selected ChipNDale cell as argument, extracts the cell using Sinix, translates the resulting cellType into a Mint flat world, and writes on the Mint viewer the statistics of the creation of the Mint sets. The Mint.Circuit created is available for simulation as CDMint.circuit.
Running Mint
1. Bringover -p [DATools]<DATools6.1>Top>Mint.df
2. Type Mint to the Commander.
Limitations
Mint is not very good with analogic designs, as it assumes that a fet is simply either open or close. Consequently, smart and tricky fet assembly will probaly result in oscillations, traducing the fact that neither the fets fully open nor fully closed reaches a equilibrium.
Example
An example is available to show the current state of the program.