~
BEGIN
debugCircuit: Mint.Circuit;
verbose: BOOLEAN ← FALSE;
maxNumber: NAT ← 10;
ExtractAndPrepare:
PROC [mode: Sinix.Mode, comm: CDSequencer.Command]
RETURNS[circuit: Mint.Circuit, instance:
CD.Instance] ~ {
IF mode=
NIL
THEN {
TerminalIO.WriteRope ["technology unknown.\n"];
RETURN
};
FOR all:
CD.InstanceList ← CDOps.InstList [comm.design], all.rest
WHILE all #
NIL
DO
IF all.first.selected
THEN {
fixedV: Mint.NodeList;
coreCell: Core.CellType;
isLayout: BOOLEAN ← mode#Sisyph.mode;
instance ← all.first;
coreCell ← NARROW[SinixOps.ExtractCDInstance [instance, comm.design, mode].result];
IF isLayout THEN WriteCapa.WriteWireCapa[coreCell, comm.design.technology.key];
WriteCapa.WriteWireCapa[coreCell, comm.design.technology.key];
circuit ← Mint.InputData[coreCell, isLayout];
fixedV ← Mint.BuildNodeList["public.Vdd", NIL, circuit];
Mint.SetNode[fixedV.first, TRUE];
fixedV ← Mint.BuildNodeList["PadVdd", fixedV, circuit]; -- if there is no PadAlims,
Mint.SetNode[fixedV.first, TRUE];
fixedV ← Mint.BuildNodeList["public.Gnd", fixedV, circuit];
Mint.SetNode[fixedV.first, FALSE];
fixedV ← Mint.BuildNodeList["PadGnd", fixedV, circuit]; -- they will be ignored.
Mint.SetNode[fixedV.first, FALSE];
Mint.PrepareSets[circuit, fixedV];
RETURN;
};
ENDLOOP
};
ShowSetList:
PROC [decoration: SinixOps.Decoration, design:
CD.Design, instance: CD.Instance, root: Core.CellType, setList: Mint.SetList] ~ {
flatWires: LIST OF SinixOps.FlatWireRec ← NIL;
FOR inode: Mint.NodeList ← setList.first.lNodes, inode.rest
UNTIL inode=
NIL
DO
flatWires ← CONS[inode.first.flatWire^, flatWires];
ENDLOOP;
FOR iSetList: Mint.SetList ← setList, iSetList.rest
UNTIL iSetList.rest=
NIL
DO
set1: Mint.Set ← iSetList.first;
set2: Mint.Set ← iSetList.rest.first;
FOR inode: Mint.NodeList ← set1.inList, inode.rest
UNTIL inode=
NIL
DO
found: BOOLEAN ← FALSE;
FOR inode2: Mint.NodeList ← set2.lNodes, inode2.rest
UNTIL inode2=
NIL
DO
IF inode2.first=inode.first THEN {found ← TRUE; EXIT};
ENDLOOP;
IF found THEN flatWires ← CONS[inode.first.flatWire^, flatWires];
ENDLOOP;
ENDLOOP;
SinixOps.HighlightNets[decoration, design, instance, root, flatWires];
};
ExtractAndTiming:
PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
worst: Mint.ps;
setList: Mint.SetList;
circuit: Mint.Circuit;
clkList: Mint.NodeList;
instance: CD.Instance;
[circuit, instance] ← ExtractAndPrepare[mode, comm];
clkList ← LIST[ Mint.NodeFromRope[clkName, circuit]];
[worst, setList] ← Mint.MaxFreqEvaluate[circuit, clkList, 0.0];
IO.PutF[Mint.StdOut, "longest time: %4.1f\n", IO.real[worst]];
ShowSetList[mode.decoration, comm.design, instance, circuit.rootCell, setList];
Mint.KillCircuit[circuit];
};
ExtractAndCheck:
PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
circuit: Mint.Circuit ← ExtractAndPrepare[mode, comm].circuit;
Mint.CheckLibrary[circuit];
debugCircuit ← circuit;
};
ExtractAndMint: PROC [mode: Sinix.Mode, comm: CDSequencer.Command] ~ {
circuit: Mint.Circuit ← ExtractAndPrepare[mode, comm].circuit;
IF verbose THEN Mint.OutputResults[circuit];
[] ← Mint.MaxCapa[circuit, maxNumber];
debugCircuit ← circuit;
};
TimingFromLayout:
PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
mode: Sinix.Mode ← SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["TimingLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndTiming[mode, comm];
TerminalIO.WriteRope ["Timing finished.\n"];
};
TimingFromSchematics:
PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
TerminalIO.WriteRope ["TimingSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndTiming[Sisyph.mode, comm];
TerminalIO.WriteRope ["Timing finished.\n"];
};
CheckFromLayout:
PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
mode: Sinix.Mode ← SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["CheckLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndCheck[mode, comm];
TerminalIO.WriteRope ["Check finished.\n"];
};
CheckFromSchematics:
PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
TerminalIO.WriteRope ["CheckSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndCheck[Sisyph.mode, comm];
TerminalIO.WriteRope ["Check finished.\n"];
};
MintFromLayout: PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
mode: Sinix.Mode ← SinixOps.GetExtractMode[comm.design.technology];
TerminalIO.WriteRope ["MintLayout\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndMint[mode, comm];
TerminalIO.WriteRope ["Mint input finished.\n"];
};
MintFromSchematics: PROC [comm: CDSequencer.Command] ~ {
Called by ChipNDale upon activation of the command.
abort: REF BOOL ← NEW [BOOL←FALSE];
TerminalIO.WriteRope ["MintSchematics\n"];
CDProperties.PutDesignProp [comm.design, $MintCmdDir];
ExtractAndMint[Sisyph.mode, comm];
TerminalIO.WriteRope ["Mint input finished.\n"];
};
clkName: Rope.ROPE ← "public.CK";
CDSequencer.ImplementCommand [key: $MintLayoutSel, proc: MintFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Mint", key: $MintLayoutSel];
CDSequencer.ImplementCommand [key: $MintSchemSel, proc: MintFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Mint", key: $MintSchemSel];
CDSequencer.ImplementCommand [key: $CheckLayoutSel, proc: CheckFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Check", key: $CheckLayoutSel];
CDSequencer.ImplementCommand [key: $CheckSchemSel, proc: CheckFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Check", key: $CheckSchemSel];
CDSequencer.ImplementCommand [key: $TimingLayoutSel, proc: TimingFromLayout, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Layout->Timing", key: $TimingLayoutSel];
CDSequencer.ImplementCommand [key: $TimingSchemSel, proc: TimingFromSchematics, queue: doQueue];
CDMenus.CreateEntry [menu: $ProgramMenu, entry: "Schema->Timing", key: $TimingSchemSel];
TerminalIO.WriteRope ["CDMint package loaded.\n"];