DIRECTORY IO, LichenDataStructure, LichenSetTheory; LichenDataOps: CEDAR DEFINITIONS = BEGIN OPEN LichenDataStructure, LichenSetTheory; EnsureAllIn: PROC [design: Design]; EnsurePublic: PROC [ct: CellType]; EnsurePrivate: PROC [ct: CellType]; ExpansionKnown: PROC [ct: CellType] RETURNS [known: BOOL]; AssertionOp: TYPE = {ignore, report, check, establish}; MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check]; FailableAssertionOp: TYPE = AssertionOp [report .. check]; CheckDesign: PROC [design: Design, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp]; CheckCellType: PROC [ct: CellType, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; CheckCellTypes: PROC [cts: Set--of CellType--, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; NoteChange: PROC [cellType: CellType]; AddPort: PROC [p: PortPrivate _ []] RETURNS [port: Port]; FullyAddPort: PROC [p: PortPrivate _ [], andReportConnectionTo: CellInstance _ NIL] RETURNS [port: Port, connection: Wire _ NIL]; RemovePort: PROC [port: Port]; AddEdge: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; AddEdges: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; RemoveEdge: PROC [e: Edge]; RemoveEdges: PROC [e: Edge]; UnlinkPort: PROC [ci: CellInstance, port: Port]; Instantiate: PROC [type, containingCT: CellType, other: Assertions _ NIL] RETURNS [ci: CellInstance]; FullyInstantiate: PROC [type, containingCT: CellType, other: Assertions _ NIL] RETURNS [ci: CellInstance]; CreateWire: PROC [containingCT: CellType, containingWire: Wire _ NIL, other: Assertions _ NIL, copy: Wire _ NIL] RETURNS [w: Wire]; CreateIntermediary: PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, other: Assertions _ NIL] RETURNS [im: Intermediary]; KnowVertexName: PROC [v: Vertex, name: ROPE]; DeleteVertex: PROC [v: Vertex]; IsMirror: PROC [v: CellInstance] RETURNS [isMirror: BOOL]; AddMirror: PROC [CellType]; MergeNets: PROC [net1, net2: Wire] RETURNS [merged, doomed: Wire]; MakeArrayConnection: PROC [ct: CellType, d: Dim, lowRange: Range2, rp1, rp2: RoledPort]; SetArrayPort: PROC [a: Array, index: ArrayIndex, ep, ap: Port]; CrossATie: PROC [ct: CellType, d: Dim, fromP: Port, fromS: End] RETURNS [toP: Port]; ComputeComplete: PROC [j: Joint, tie: Tie, cji: NAT] RETURNS [complete: BOOL]; Log: PROC [fmt: ROPE, v1, v2, v3, v4, v5: REF ANY _ NIL]; END. lLichenDataOps.Mesa Last Edited by: Spreitzer, June 11, 1986 4:13:08 pm PDT Mike Spreitzer June 26, 1986 4:53:12 pm PDT = A ct B deisgn : EnsurePrivate[ct] Make sure interface is fully defined. Make sure the internals are as known as possible. Do we know how this cell type is decomposed? Adds as last child of parent, if any. Adds dummy wires by instances. Will introduce Intermediaries, if necessary. Removes ancestor Intermediaries that have no children. Remove the edge for given port. Adds dummy wires. As last child of containingWire, if any. With same structure as copy, if given, leaf structure otherwise. Κ– "cedar" style˜code™J™7K™+—K˜KšΟk œœ'˜3K˜šΠbx œœ œ˜"K˜Kšœœ&˜0K˜šΟn œœ˜#KšœΟmœ œ™#—K˜šŸ œœ˜"K™%—K˜šŸ œœ˜#K™1—K˜šŸœœœ œ˜:K™,—K˜Kšœ œ&˜7Kšœœ!˜AKšœœ!˜:K˜KšŸ œœR˜cKšŸ œœqœœ˜‘Kš Ÿœœ Οcœcœœ˜K˜KšŸ œœ˜&K˜šŸœœœ˜9K™%—š Ÿ œœ=œœ!œ˜K™—KšŸ œœ˜KšŸœœœœ˜?šŸœœœœ˜@K™,—KšŸ œœ ˜šŸ œœ ˜K™6—šŸ œœ ˜0K™—KšŸ œœ4œœ˜ešŸœœ4œœ˜jK™—š Ÿ œœ1œœœœ ˜ƒKšœ(™(K™@—KšŸœœ\œœ˜”KšŸœœœ˜-KšŸ œœ ˜KšŸœœœ œ˜:KšŸ œœ ˜KšŸ œœœ˜BKšŸœœ?˜XKšŸ œœ-˜?KšŸ œœ1œ ˜TKš Ÿœœœœ œ˜NK˜Kš Ÿœœœœœœ˜9K˜Kšœ˜——…— ΐE