LichenDataStructure:
CEDAR
DEFINITIONS
IMPORTS HashTable, IntHashTable =
BEGIN OPEN LichenSetTheory;
nyet: ERROR --not yet implemented--;
Warning: SIGNAL [msg: ROPE, v1, v2, v3, v4, v5: REF ANY ← NIL];
Error: ERROR [msg: ROPE, v1, v2, v3, v4, v5: REF ANY ← NIL];
LORA: TYPE = LIST OF REF ANY;
LOLORA: TYPE = LIST OF LORA;
ROPE: TYPE = Rope.ROPE;
RopeList: TYPE = LIST OF ROPE;
Assertions: TYPE = Asserting.Assertions;
RefTable: TYPE = HashTable.Table;
CreateRefTable:
PROC
RETURNS [rt: RefTable]
= INLINE {rt ← HashTable.Create[]};
IntTable: TYPE = IntHashTable.Table;
CreateIntTable:
PROC
RETURNS [it: IntTable]
= INLINE {it ← IntHashTable.Create[]};
GraphID: TYPE = {A, B, Unspecified};
RealGraphID: TYPE = GraphID[A .. B];
OtherGraph: ARRAY RealGraphID OF RealGraphID = [A: B, B: A];
graphIDToRope: ARRAY GraphID OF ROPE;
Color: TYPE = INT;
noColor: Color = LAST[Color];
someColor: Color = 871;
FilterColor:
PROC [color: Color]
RETURNS [filtered: Color] =
INLINE {
filtered ← IF color # noColor THEN color ELSE someColor};
Design: TYPE = REF DesignPrivate;
DesignPrivate:
TYPE =
RECORD [
cellTypes: Set,
other: Assertions ← NIL,
allKnown: BOOL ← FALSE];
nameReln: ATOM; --relative to narrowest enclosing scope
Describe: PROC [subject: REF ANY, relativeTo: REF ANY ← NIL, nameGen: NameGenerator ← NIL] RETURNS [ROPE];
NameGenerator: TYPE = REF NameGeneratorPrivate;
NameGeneratorPrivate:
TYPE =
RECORD [
GenerateName: PROC [data, subject: REF ANY] RETURNS [ROPE],
data: REF ANY ← NIL
];
EnumerateCellTypes: PROC [design: Design, Consume: PROC [CellType]];
CellClass: TYPE = REF CellClassPrivate;
CellClassPrivate:
TYPE =
RECORD [
DefinePrivates: PROC [CellType]
];
CellType: TYPE = REF CellTypePrivate;
CellTypePrivate:
TYPE =
RECORD [
class: CellClass,
designs: Set,
publicKnown, privateKnown: BOOL ← FALSE,
wasntNormalized:
BOOL ←
FALSE,
Leftover
port: Port ← NIL,
asUnorganized: Unorganized ← NIL,
asArray: Array ← NIL,
firstInstance, lastInstance: CellInstance ← NIL,
firstArray, lastArray: CellType ← NIL,
useCount: INT ← 0 --#instances + #arrays--,
otherPublic, otherPrivate: Assertions ← NIL,
color: Color ← noColor];
EnumeratePorts: PROC [cellType: CellType, Consume: PROC [Port]];
EnumerateInstances: PROC [cellType: CellType, Consume: PROC [CellInstance]];
EnumerateArrays: PROC [cellType: CellType, Consume: PROC [CellType]];
partsByNameKey:
ATOM;
private CellType b Mapper(ROPE b Vertex)
PortList: TYPE = LIST OF Port;
Port: TYPE = REF PortPrivate;
PortPrivate:
TYPE =
RECORD [
next, prev: Port,
firstChild, lastChild: Port,
parent: REF ANY--UNION [Port, CellType]--,
wire: Wire ← NIL,
other: Assertions ← NIL,
color: Color ← noColor];
PortCCT: PROC [port: Port] RETURNS [containingCT: CellType];
FirstChildPort:
PROC [port: Port]
RETURNS [child: Port]
= INLINE {child ← port.firstChild};
NextChildPort:
PROC [child: Port]
RETURNS [sibling: Port]
= INLINE {sibling ← child.next};
PortIndex: PROC [parent, child: Port] RETURNS [index: INT];
SubPort: PROC [parent: Port, index: INT] RETURNS [child: Port];
Unorganized: TYPE = REF UnorganizedPrivate;
UnorganizedPrivate:
TYPE =
RECORD [
internalWire: Wire ← NIL,
containedInstances: Set--of CellInstance-- ← NIL,
mirror: CellInstance ←
NIL
--the outside world, as seen from the inside
AM1: A mirror is not entered in containedInstances.
AM2: A mirror is not counted as an instance of its type.
AM3: mirror.type = mirror.container
];
Vertex: TYPE = REF VertexPrivate;
VertexPrivate:
TYPE =
RECORD [
containingCT: CellType,
QNext: Vertex ← notInQ,
colorNext, equiv: Vertex ← NIL,
firstEdge, lastEdge: Edge ←
NIL,
The connections to/from cells.
AI1: The edges are in the following order: first, the cellward ones, if any, in any order, then the wireward ones, ordered by port.
other: Assertions ← NIL,
oldColor, curColor: Color ← noColor,
graph: GraphID ← Unspecified,
unique, suspect: BOOL ← FALSE,
variant:
SELECT class: VertexClass
FROM
cell => [
type: CellType ← NIL,
nextInstance, prevInstance: CellInstance ← NIL
],
intermediate => [
port: Port
],
wire => [
containingWire: Wire ← NIL,
next, prev: Wire ← NIL, --Siblings
firstChild, lastChild: Wire ← NIL
],
ENDCASE];
VertexClass: TYPE = {cell, intermediate, wire};
CellInstance: TYPE = REF cell VertexPrivate;
Intermediary: TYPE = REF intermediate VertexPrivate;
Wire: TYPE = REF wire VertexPrivate;
WireIndex: PROC [parent, child: Wire] RETURNS [index: INT];
SubWire: PROC [parent: Wire, index: INT] RETURNS [child: Wire];
EnumeratePortAndWire: PROC [port: Port, wire: Wire, Consume: PROC [Port, Wire]];
FirstChildWire:
PROC [parent: Wire]
RETURNS [child: Wire]
= INLINE {child ← parent.firstChild};
NextChildWire:
PROC [child: Wire]
RETURNS [sibling: Wire]
= INLINE {sibling ← child.next};
Edge: TYPE = REF EdgePrivate;
EdgePrivate:
TYPE =
RECORD [
sides: ARRAY GraphDirection OF RECORD [v: Vertex, next, prev: Edge],
port: Port --what the wireward vertex is connected to
];
GraphDirection: TYPE = {cellward, wireward};
OppositeDirection: ARRAY GraphDirection OF GraphDirection = [cellward: wireward, wireward: cellward];
notInQ: Vertex --don't look:-- = NIL --you looked!--;
endOfQ: Vertex;
EnumerateImmediateEdges:
PROC [v: Vertex,
Consume:
PROC [Port, Vertex, Edge], filter:
ARRAY GraphDirection
OF
BOOL ←
ALL[
TRUE], order: Order ← any];
the Port is the wireward one.
EnumerateImmediateConnections: PROC [v: Vertex, Consume: PROC [Port, Vertex], filter: ARRAY GraphDirection OF BOOL ← ALL[TRUE], order: Order ← any];
EnumerateTransitiveConnections: PROC [v: Vertex, Consume: PROC [Port, Vertex]];
EnumerateTopEdges: PROC [ci: CellInstance, Consume: PROC [Port, Wire, Edge]];
EnumerateTopConnections: PROC [ci: CellInstance, Consume: PROC [Port, Wire]];
EnumerateNeighboringVertices: PROC [v: Vertex, Consume: PROC [Vertex], filter: ARRAY GraphDirection OF BOOL ← ALL[TRUE]];
FindImmediateConnection: PROC [cellward: Vertex, port: Port, hint: Order ← any] RETURNS [w: Vertex];
FindImmediateEdge: PROC [cellward: Vertex, port: Port, hint: Order ← any] RETURNS [w: Vertex, e: Edge];
FindTransitiveConnection: PROC [cellward: Vertex, port: Port] RETURNS [w: Wire];
ImParent: PROC [im: Intermediary] RETURNS [v: Vertex];
Order: TYPE = {forward, backward, any};
Array: TYPE = REF ArrayPrivate;
ArrayPrivate:
TYPE =
RECORD [
eltType: CellType ← NIL,
nextArray, prevArray: CellType ← NIL,
size: Size2 ← ALL[1],
joints: ARRAY Dim--in which we are joining-- OF RefSeq--of Joint-- ← ALL[NIL],
jointsPeriod: Size2 ← ALL[1],
portConnections: RefTable
--ap
array.port
b apc: ArrayPortConnections--,
redundant with porting.
porting: RefTable
--ep
eltType.port
b p: Porting-- ←
NIL
porting[p] gives port connections for e[f, b].p, for all f, b on edge of array.
];
Dim--ension--: TYPE = {Foo, Bar};
OtherDim: ARRAY Dim OF Dim = [Foo: Bar, Bar: Foo];
Size2: TYPE = ARRAY Dim OF INT;
Range: TYPE = RECORD [min, maxPlusOne: INT];
Range2: TYPE = ARRAY Dim OF Range;
Joint: TYPE = REF JointPrivate;
JointPrivate:
TYPE =
RECORD [
size2: Size2,
size: INT--P size2--,
nrp: INT--number of roled ports--,
ties: Set,
toTie: ARRAY End OF RefTable--side of joint b Port b Tie--,
toRole: ARRAY End OF RefTable--side b port b roledPort--,
roles: VarRefSeq--index b roledPort--
];
Tie: TYPE = REF TiePrivate;
TiePrivate:
TYPE =
RECORD [
ports: RoledPortDataList ← NIL,
n: INT--number of roledPorts in this tie-- ← 0,
mindex: INT--smallest index among this ties ports-- ← 0,
completion: Completion ← NIL
];
RoledPortDataList: TYPE = LIST OF RoledPortData;
RoledPortData: TYPE = REF RoledPortDataPrivate;
RoledPortDataPrivate:
TYPE =
RECORD [
port: Port,
side: End,
index: NAT,
links: Links ← NIL
];
RoledPort: TYPE = RECORD [side: End, port: Port];
Links: TYPE = REF LinksPrivate;
LinksPrivate:
TYPE =
RECORD [
linkSize: NAT,
negLinkSize, negLgLinksPerWord: INTEGER,
lgLinksPerWord: Sublg,
words: SEQUENCE length: NAT OF WORD
];
words[cji ShiftRight lgLinksPerWord] ShiftRight (linkSize*(cji MaskLast lgLinksPerWord)) MaskLast linkSize gives index of another roledPort connected to this one at ji
where:
cji = <size[Foo], size[Bar]> ¥ <ji[Foo], ji[Bar]>
`¥' is APL's `decode'
size is the number of instances of the containing joint
ji is the index of a particular instance of the joint
GetRoot: PROC [j: Joint, rp: RoledPortData, cji: NAT] RETURNS [root: NAT];
GetNext: PROC [j: Joint, rp: RoledPortData, cji: NAT] RETURNS [next: NAT];
Sublg: TYPE = NAT [0 .. Basics.logBitsPerWord];
Completion: TYPE = REF CompletionPrivate;
CompletionPrivate:
TYPE =
RECORD [
nIncomplete: INT ← 0,
complete: PACKED SEQUENCE length: NAT OF BOOL
];
complete[cji] { all connections present at instance ji of containing joint
GetArrayJoint:
PROC [a: Array, d: Dim, phase: ArrayIndex]
RETURNS [j: Joint]
= INLINE {j ← NARROW[a.joints[d][ArrayJointIndex[a, phase]]]};
ArrayJointIndex: PROC [a: Array, phase: ArrayIndex] RETURNS [i: INT] = INLINE {i ← phase[Foo]*a.jointsPeriod[Bar] + phase[Bar]};
Porting: TYPE = REF ANY --actually UNION [{notPorted, unknownPorting}, DetailedPorting]--;
notPorted: Porting;
unknownPorting: Porting;
DetailedPorting: TYPE = REF DetailedPortingRep;
DetailedPortingRep:
TYPE =
RECORD [
corners:
ARRAY End
--Foo--
OF
ARRAY End
--Bar--
OF Port,
e[Foo.LAST, Bar.LAST].p é a.q { porting[p].corners[high][high] = q
NIL means elt port not connected to any array port.
sideIndices:
ARRAY End
OF
ARRAY Dim
OF SideIndex,
sideIndices[low][Foo] covers [f, b] f = FIRST[Foo] & b (FIRST[BAR] .. LAST[BAR])
slots: SEQUENCE length: NAT OF Port];
End: TYPE = {low, high};
OtherEnd: ARRAY End OF End = [low: high, high: low];
SideIndex: TYPE = RECORD [same: BOOL, firstSlot: NAT];
ArrayPortConnections: TYPE = REF ArrayPortConnectionsPrivate;
ArrayPortConnectionsPrivate: TYPE = ARRAY End OF ARRAY Dim OF SideConnection;
SideConnection: TYPE = IntTable--index[other dim] b elt Port--;
ArraySocketList: TYPE = LIST OF ArraySocket;
ArraySocket: TYPE = RECORD [ai: ArrayIndex, p: Port];
ArrayIndex: TYPE = ARRAY Dim OF INT;
GetArrayPort: PROC [a: Array, index: ArrayIndex, ep: Port] RETURNS [arrayPort: Port];
RefSeq: TYPE = REF RefSequence;
RefSequence:
TYPE =
RECORD [
elts: SEQUENCE length: NAT OF REF ANY];
CreateRefSeq:
PROC [len:
NAT]
RETURNS [rs: RefSeq]
= INLINE {rs ← NEW [RefSequence[len]]};
VarRefSeq: TYPE = REF VarRefSequence;
VarRefSequence:
TYPE =
RECORD [
length: NAT,
refs: RefSeq];
CreateVarRefSeq:
PROC [size:
NAT ← 12]
RETURNS [vrs: VarRefSeq]
= INLINE {vrs ← NEW [VarRefSequence ← [0, CreateRefSeq[size]]]};
BoolSeq: TYPE = REF BoolSequence;
BoolSequence: TYPE = RECORD [elts: PACKED SEQUENCE length: NAT OF BOOL];
CreateBoolSeq:
PROC [len:
NAT, b0:
BOOL ←
FALSE]
RETURNS [bs: BoolSeq]
= INLINE {bs ← NEW [BoolSequence[len]]; FOR i: NAT IN [0 .. len) DO bs[i] ← b0 ENDLOOP};
FloorDiv: PROC [num, den: INT] RETURNS [quot: INT];
CeilDiv: PROC [num, den: INT] RETURNS [quot: INT];
END.