<> <> <> DIRECTORY IO, LichenDataStructure, LichenSetTheory; LichenDataOps: CEDAR DEFINITIONS = BEGIN OPEN LichenDataStructure, LichenSetTheory; EnsureAllIn: PROC [design: Design]; <<= >> EnsurePublic: PROC [ct: CellType]; <> EnsurePrivate: PROC [ct: CellType]; <> ExpansionKnown: PROC [ct: CellType] RETURNS [known: BOOL]; <> AssertionOp: TYPE = {ignore, report, check, establish}; MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check]; FailableAssertionOp: TYPE = AssertionOp [report .. check]; CheckDesign: PROC [design: Design, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp]; CheckCellType: PROC [ct: CellType, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; CheckCellTypes: PROC [cts: Set--of CellType--, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL _ TRUE]; NoteChange: PROC [cellType: CellType]; AddPort: PROC [p: PortPrivate _ []] RETURNS [port: Port]; <> FullyAddPort: PROC [p: PortPrivate _ [], andReportConnectionTo: CellInstance _ NIL] RETURNS [port: Port, connection: Wire _ NIL]; <> RemovePort: PROC [port: Port]; AddEdge: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; AddEdges: PROC [vs: ARRAY GraphDirection OF Vertex, port: Port]; <> RemoveEdge: PROC [e: Edge]; RemoveEdges: PROC [e: Edge]; <> UnlinkPort: PROC [ci: CellInstance, port: Port]; <> Instantiate: PROC [type, containingCT: CellType, other: Assertions _ NIL] RETURNS [ci: CellInstance]; FullyInstantiate: PROC [type, containingCT: CellType, other: Assertions _ NIL] RETURNS [ci: CellInstance]; <> CreateWire: PROC [containingCT: CellType, containingWire: Wire _ NIL, other: Assertions _ NIL, copy: Wire _ NIL] RETURNS [w: Wire]; <> <> CreateIntermediary: PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, other: Assertions _ NIL] RETURNS [im: Intermediary]; KnowVertexName: PROC [v: Vertex, name: ROPE]; DeleteVertex: PROC [v: Vertex]; IsMirror: PROC [v: CellInstance] RETURNS [isMirror: BOOL]; AddMirror: PROC [CellType]; MergeNets: PROC [net1, net2: Wire] RETURNS [merged, doomed: Wire]; MakeArrayConnection: PROC [ct: CellType, d: Dim, lowRange: Range2, rp1, rp2: RoledPort]; SetArrayPort: PROC [a: Array, index: ArrayIndex, ep, ap: Port]; CrossATie: PROC [ct: CellType, d: Dim, fromP: Port, fromS: End] RETURNS [toP: Port]; ComputeComplete: PROC [j: Joint, tie: Tie, cji: NAT] RETURNS [complete: BOOL]; Log: PROC [fmt: ROPE, v1, v2, v3, v4, v5: REF ANY _ NIL]; END.