LichenDataImpl:
CEDAR
PROGRAM
IMPORTS Asserting, HashTable, IO, LichenDataStructure, LichenSetTheory, Rope, ViewerIO
EXPORTS LichenDataStructure, LichenDataOps =
BEGIN OPEN LichenSetTheory, LichenDataStructure;
EnumerateCellTypes:
PUBLIC
PROC [design: Design,
Consume:
PROC [CellType]] = {
PerCellType: PROC [elt: REF ANY] = {Consume[NARROW[elt]]};
design.cellTypes.Enumerate[PerCellType]};
endOfQ: PUBLIC Vertex ← NEW [VertexPrivate.intermediate];
EnumerateImmediateEdges:
PUBLIC
PROC [v: Vertex,
Consume:
PROC [Port, Vertex, Edge], filter:
ARRAY GraphDirection
OF
BOOL ←
ALL[
TRUE], order: Order ← any] = {
nextEdge: Edge ←
SELECT order
FROM
--these depend on AI1
forward, any => v.firstEdge,
backward => v.lastEdge,
ENDCASE => ERROR;
FOR e: Edge ← nextEdge, nextEdge
WHILE e #
NIL
DO
selfward: GraphDirection =
SELECT v.class
FROM
cell => cellward,
wire => wireward,
intermediate =>
SELECT v
FROM
e.sides[wireward].v => wireward,
e.sides[cellward].v => cellward,
ENDCASE => ERROR,
ENDCASE => ERROR;
away: GraphDirection = OppositeDirection[selfward];
w: Vertex = e.sides[away].v;
IF v # e.sides[selfward].v THEN ERROR;
IF v.class # intermediate AND v.class = w.class THEN ERROR Error["Broken"];
nextEdge ←
SELECT order
FROM
--these depend on AI1
forward, any => e.sides[selfward].next,
backward => e.sides[selfward].prev,
ENDCASE => ERROR;
IF filter[away] THEN Consume[e.port, w, e];
ENDLOOP;
};
EnumerateImmediateConnections:
PUBLIC
PROC [v: Vertex,
Consume:
PROC [Port, Vertex], filter:
ARRAY GraphDirection
OF
BOOL ←
ALL[
TRUE], order: Order ← any] = {
Filter: PROC [port: Port, w: Vertex, e: Edge] = {Consume[port, w]};
EnumerateImmediateEdges[v, Filter, filter, order];
};
EnumerateNeighboringVertices:
PUBLIC
PROC [v: Vertex,
Consume:
PROC [Vertex], filter:
ARRAY GraphDirection
OF
BOOL ←
ALL[
TRUE]] = {
Filter: PROC [port: Port, w: Vertex, e: Edge] = {Consume[w]};
EnumerateImmediateEdges[v, Filter, filter];
};
EnumerateTransitiveConnections:
PUBLIC
PROC [v: Vertex,
Consume:
PROC [Port, Vertex]] = {
WITH v
SELECT
FROM
wire: Wire => {
WireWork:
PROC [wire: Wire,
Consume:
PROC [Port, Vertex]] = {
CellStart:
PROC [port: Port, w: Vertex] = {
WITH w
SELECT
FROM
ci: CellInstance => Consume[port, ci];
im: Intermediary => {
CellFinish:
PROC [parent: Port, u: Vertex] = {
WITH u
SELECT
FROM
ci: CellInstance => Consume[port, ci];
im: Intermediary => EnumerateImmediateConnections[im, CellFinish, [cellward: TRUE, wireward: FALSE]];
wire: Wire => ERROR;
ENDCASE => ERROR;
};
EnumerateImmediateConnections[im, CellFinish, [cellward: TRUE, wireward: FALSE]];
};
wire: Wire => ERROR;
ENDCASE => ERROR;
};
EnumerateImmediateConnections[wire, CellStart];
IF wire.containingWire #
NIL
THEN {
index: INT = WireIndex[wire.containingWire, wire];
Filter:
PROC [parent: Port, w: Vertex] = {
port: Port = SubPort[parent, index];
Consume[port, w]};
WireWork[wire.containingWire, Filter];
};
};
WireWork[wire, Consume];
};
im: Intermediary => ERROR;
ci: CellInstance => {
Elaborate: PROC [port: Port, wire: Wire] = {EnumeratePortAndWire[port, wire, Consume]};
EnumerateTopConnections[ci, Elaborate];
};
ENDCASE => ERROR;
};
EnumerateTopEdges:
PUBLIC
PROC [ci: CellInstance,
Consume:
PROC [Port, Wire, Edge]]= {
Work:
PROC [port: Port, v: Vertex, e: Edge] = {
WITH v
SELECT
FROM
wire: Wire => Consume[port, wire, e];
im: Intermediary => EnumerateImmediateEdges[im, Work, [cellward: FALSE, wireward: TRUE]];
ci: CellInstance => ERROR;
ENDCASE => ERROR;
};
EnumerateImmediateEdges[ci, Work];
};
EnumerateTopConnections:
PUBLIC
PROC [ci: CellInstance,
Consume:
PROC [Port, Wire]]= {
Filter: PROC [port: Port, w: Wire, e: Edge] = {Consume[port, w]};
EnumerateTopEdges[ci, Filter];
};
FindImmediateConnection:
PUBLIC
PROC [cellward: Vertex, port: Port, hint: Order ← any]
RETURNS [w: Vertex] = {
w ← FindImmediateEdge[cellward, port, hint].w;
};
FindImmediateEdge:
PUBLIC
PROC [cellward: Vertex, port: Port, hint: Order ← any]
RETURNS [w: Vertex, e: Edge] = {
ENABLE Escape => CONTINUE;
Consume:
PROC [tp: Port, tw: Vertex, te: Edge] = {
IF tp = port THEN {w ← tw; e ← te; Escape};
};
EnumerateImmediateEdges[cellward, Consume, [cellward: FALSE, wireward: TRUE], hint];
ERROR--not found--;
};
Escape: ERROR = CODE;
FindTransitiveConnection:
PUBLIC
PROC [cellward: Vertex, port: Port]
RETURNS [w: Wire] = {
ENABLE Escape => CONTINUE;
Tryit:
PROC [p: Port, v: Vertex] = {
IF port = p THEN {w ← NARROW[v]; Escape};
};
EnumerateTransitiveConnections[cellward, Tryit];
ERROR--not found--;
};
ImParent:
PUBLIC
PROC [im: Intermediary]
RETURNS [v: Vertex] = {
See: PROC [w: Vertex] = {v ← w};
EnumerateNeighboringVertices[im, See, [cellward: TRUE, wireward: FALSE]];
};
EnumeratePorts:
PUBLIC
PROC [cellType: CellType,
Consume:
PROC [Port]] = {
Work:
PROC [port: Port, wire: Wire, wired:
BOOL] = {
subPort: Port ← port.firstChild;
subWire: Wire ← IF wired THEN wire.firstChild ELSE NIL;
IF port.wire # wire THEN ERROR Error["Broken"];
Consume[port];
WHILE subPort #
NIL
DO
IF NOT wired THEN subWire ← subPort.wire ELSE IF subWire = NIL THEN ERROR Error["Broken"];
Work[subPort, subWire, subWire # NIL];
subPort ← subPort.next;
IF wired THEN subWire ← subWire.next;
ENDLOOP;
IF wired AND subWire # NIL THEN ERROR Error["Broken"];
};
Work[cellType.port, cellType.port.wire, cellType.port.wire # NIL];
IF cellType.port.next # NIL THEN ERROR Error["Broken"];
};
EnumerateInstances:
PUBLIC
PROC [cellType: CellType,
Consume:
PROC [CellInstance]] = {
FOR ci: CellInstance ← cellType.firstInstance, ci.nextInstance
WHILE ci #
NIL
DO
Consume[ci];
ENDLOOP;
};
EnumeratePortAndWire:
PUBLIC
PROC [port: Port, wire: Wire,
Consume:
PROC [Port, Wire]] = {
Consume[port, wire];
port ← port.firstChild;
wire ← wire.firstChild;
WHILE port #
NIL
AND wire #
NIL
DO
EnumeratePortAndWire[port, wire, Consume];
port ← port.next;
wire ← wire.next;
ENDLOOP;
IF port # NIL OR wire # NIL THEN ERROR Error["Broken"];
};
WireIndex:
PUBLIC
PROC [parent, child: Wire]
RETURNS [index:
INT] = {
index ← 0;
FOR x: Wire ← parent.firstChild, x.next WHILE x # child DO index ← index + 1 ENDLOOP;
index ← index;
};
SubWire:
PUBLIC
PROC [parent: Wire, index:
INT]
RETURNS [child: Wire] = {
FOR child ← parent.firstChild, child.next WHILE index > 0 DO index ← index - 1 ENDLOOP;
};
PortCCT:
PUBLIC
PROC [port: Port]
RETURNS [containingCT: CellType] = {
DO
WITH port.parent
SELECT
FROM
ct: CellType => RETURN [ct];
p: Port => port ← p;
ENDCASE => ERROR;
ENDLOOP;
};
PortIndex:
PUBLIC
PROC [parent, child: Port]
RETURNS [index:
INT] = {
index ← 0;
FOR x: Port ← parent.firstChild, x.next WHILE x # child DO index ← index + 1 ENDLOOP;
index ← index;
};
SubPort:
PUBLIC
PROC [parent: Port, index:
INT]
RETURNS [child: Port] = {
FOR child ← parent.firstChild, child.next WHILE index > 0 DO index ← index - 1 ENDLOOP;
};
EnsureAllIn:
PUBLIC
PROC [design: Design] = {
IF design.allKnown THEN RETURN;
design.allKnown ← TRUE;
EnumerateCellTypes[design, EnsurePrivate];
};
EnsurePublic:
PUBLIC
PROC [ct: CellType] = {
IF NOT ct.publicKnown THEN ERROR Error["Broken: Found cell type with undefined interface"];
IF ct.port = NIL THEN ERROR;
};
EnsurePrivate:
PUBLIC
PROC [ct: CellType] = {
IF
NOT ct.privateKnown
THEN {
ct.class.DefinePrivates[ct];
IF NOT ct.privateKnown THEN ERROR;
};
};
ExpansionKnown:
PUBLIC
PROC [ct: CellType]
RETURNS [known:
BOOL] = {
known ← ct.asUnorganized # NIL OR ct.asArray # NIL;
};
NoteChange:
PUBLIC
PROC [cellType: CellType] = {
NULL--er, we haven't yet figured out just what to do about the fact that cell types can change--;
};
AddPort:
PUBLIC
PROC [p: PortPrivate ← []]
RETURNS [port: Port] = {
port ← NEW [PortPrivate ← p];
WITH p.parent
SELECT
FROM
pp: Port => {
port.next ← NIL;
port.prev ← pp.lastChild;
pp.lastChild ← port;
IF port.prev # NIL THEN port.prev.next ← port ELSE pp.firstChild ← port;
};
ct: CellType => {
IF ct.port # NIL THEN ERROR;
ct.port ← port;
port.next ← port.prev ← NIL;
port.other ← Asserting.Assert[nameReln, LIST[R["PORTS"]], port.other];
};
ENDCASE => ERROR;
};
R: PROC [r: ROPE] RETURNS [r2: ROPE] = INLINE {r2 ← r}--stupid goddam anachronism--;
FullyAddPort:
PUBLIC
PROC [p: PortPrivate ← [], andReportConnectionTo: CellInstance ←
NIL]
RETURNS [port: Port, connection: Wire ←
NIL] = {
ct: CellType = PortCCT[port ← AddPort[p]];
portName: ROPE = Describe[port, ct.port];
FixInstance:
PROC [ci: CellInstance] = {
instanceName: ROPE = Describe[ci, ci.containingCT].Cat["/", portName];
w: Wire = CreateWire[ci.containingCT, NIL, Asserting.Assert[nameReln, LIST[instanceName], NIL]];
AddEdge[[cellward: ci, wireward: w], port];
IF andReportConnectionTo = ci THEN connection ← w;
};
IF ct.asUnorganized #
NIL
THEN {
IF ct.asUnorganized.mirror = NIL THEN ERROR;
IF p.wire = NIL THEN ERROR;
AddEdge[[cellward: ct.asUnorganized.mirror, wireward: port.wire], port];
};
IF ct.asArray #
NIL
THEN {
NULL--we don't need to do anything--;
};
EnumerateInstances[ct, FixInstance];
};
RemovePort:
PUBLIC
PROC [port: Port] = {
WITH port.parent
SELECT
FROM
pp: Port => {
IF port.next = NIL THEN pp.lastChild ← port.prev ELSE port.next.prev ← port.prev;
IF port.prev = NIL THEN pp.firstChild ← port.next ELSE port.prev.next ← port.next;
};
ct: CellType => {
ERROR --I don't think we ever really want to Remove the root port--;
};
ENDCASE => ERROR;
};
AddEdge:
PUBLIC
PROC [vs:
ARRAY GraphDirection
OF Vertex, port: Port] = {
e: Edge = NEW [EdgePrivate ← [port: port]];
FOR dir: GraphDirection IN GraphDirection DO e.sides[dir].v ← vs[dir] ENDLOOP;
FOR side: GraphDirection
IN GraphDirection
DO
LinkEdge[vs[side], e, side];
ENDLOOP;
};
LinkEdge:
PROC [v: Vertex, e: Edge, side: GraphDirection] = {
prev, next: Edge;
SELECT side
FROM
cellward => {
prev ← IF e.port.prev # NIL THEN FindImmediateEdge[v, e.port.prev, backward].e ELSE v.lastEdge;
};
wireward => prev ← v.lastEdge;
ENDCASE => ERROR;
e.sides[side].next ← next ← IF prev # NIL THEN prev.sides[side].next ELSE NIL;
e.sides[side].prev ← prev;
IF prev = NIL THEN v.firstEdge ← e ELSE prev.sides[side].next ← e;
IF next = NIL THEN v.lastEdge ← e ELSE next.sides[side].prev ← e;
};
AddEdges:
PUBLIC
PROC [vs:
ARRAY GraphDirection
OF Vertex, port: Port] = {
rootPort: Port =
WITH vs[cellward]
SELECT
FROM
ci: CellInstance => ci.type.port,
im: Intermediary => im.port,
w: Wire => ERROR Error["Broken"],
ENDCASE => ERROR;
FindVertex:
PROC [port: Port]
RETURNS [v: Vertex] = {
cellward: Vertex;
IF port = rootPort THEN RETURN [vs[cellward]];
cellward ← FindVertex[NARROW[port.parent]];
v ← FindImmediateConnection[cellward, port];
IF v # NIL THEN RETURN;
v ← CreateIntermediary[cellward, wireward, cellward.containingCT, port];
};
immediatelyCellward: Vertex = FindVertex[NARROW[port.parent]];
AddEdge[[cellward: immediatelyCellward, wireward: vs[wireward]], port];
};
RemoveEdge:
PUBLIC
PROC [e: Edge] = {
FOR dir: GraphDirection
IN GraphDirection
DO
[e.sides[dir].v.firstEdge, e.sides[dir].v.lastEdge] ← UnlinkEdge[e.sides[dir].v.firstEdge, e.sides[dir].v.lastEdge, e, dir];
ENDLOOP;
};
UnlinkEdge:
PROC [head, tail, e: Edge, dir: GraphDirection]
RETURNS [newHead, newTail: Edge] = {
newHead ← head; newTail ← tail;
IF e.sides[dir].next # NIL THEN e.sides[dir].next.sides[dir].prev ← e.sides[dir].prev ELSE newTail ← e.sides[dir].prev;
IF e.sides[dir].prev # NIL THEN e.sides[dir].prev.sides[dir].next ← e.sides[dir].next ELSE newHead ← e.sides[dir].next;
};
RemoveEdges:
PUBLIC
PROC [e: Edge] = {
cellward: Vertex = e.sides[cellward].v;
RemoveEdge[e];
IF ISTYPE[cellward, Intermediary] AND (cellward.lastEdge = NIL OR cellward.lastEdge.sides[wireward].v = cellward--AI1 used here--) THEN RemoveEdges[cellward.firstEdge--AI1 used here--];
};
UnlinkPort:
PUBLIC
PROC [ci: CellInstance, port: Port] = {
RemoveEdge[FindImmediateEdge[ci, port].e]};
Instantiate:
PUBLIC
PROC [type, containingCT: CellType, other: Assertions ←
NIL]
RETURNS [ci: CellInstance] = {
ci ←
NEW [VertexPrivate.cell ← [
containingCT: containingCT,
other: other,
variant: cell[
type: type,
nextInstance: NIL,
prevInstance: type.lastInstance]]];
type.lastInstance ← ci;
IF ci.prevInstance # NIL THEN ci.prevInstance.nextInstance ← ci ELSE ci.type.firstInstance ← ci;
type.useCount ← type.useCount + 1;
[] ← containingCT.asUnorganized.containedInstances.UnionSingleton[ci];
NoteNewPart[ci];
};
FullyInstantiate:
PUBLIC
PROC [type, containingCT: CellType, other: Assertions ←
NIL]
RETURNS [ci: CellInstance] = {
ci ← Instantiate[type, containingCT, other];
{instanceName: ROPE = Describe[ci, ci.containingCT];
FOR port: Port ← type.port.FirstChildPort[], port.NextChildPort[]
WHILE port #
NIL
DO
portName: ROPE = Describe[port, type.port];
wireName: ROPE = Rope.Cat[instanceName, "/", portName];
w: Wire = CreateWire[ci.containingCT, NIL, Asserting.Assert[nameReln, LIST[wireName], NIL]];
AddEdge[[cellward: ci, wireward: w], port];
ENDLOOP;
ci ← ci;
}};
CreateWire:
PUBLIC
PROC [containingCT: CellType, containingWire: Wire ←
NIL, other: Assertions ←
NIL, copy: Wire ←
NIL]
RETURNS [w: Wire] = {
IF containingWire = NIL THEN containingWire ← containingCT.asUnorganized.internalWire;
w ←
NEW [VertexPrivate.wire ← [
containingCT: containingCT,
other: other,
variant: wire[
containingWire: containingWire,
next: NIL,
prev: IF containingWire#NIL THEN containingWire.lastChild ELSE NIL
]]];
IF w.prev # NIL THEN w.prev.next ← w ELSE IF containingWire#NIL THEN containingWire.firstChild ← w;
IF containingWire#NIL THEN containingWire.lastChild ← w ELSE containingCT.asUnorganized.internalWire ← w;
IF copy # NIL THEN WireCopy[copy, w];
NoteNewPart[w];
};
WireCopy:
PROC [from, to: Wire] = {
FOR child: Wire ← from.FirstChildWire[], child.NextChildWire[]
WHILE child #
NIL
DO
[] ← CreateWire[to.containingCT, to, NIL, child];
ENDLOOP;
};
CreateIntermediary:
PUBLIC
PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, other: Assertions ←
NIL]
RETURNS [im: Intermediary] = {
vs: ARRAY GraphDirection OF Vertex ← ALL[from];
vs[go] ← im ←
NEW [VertexPrivate.intermediate ← [
containingCT: containingCT,
other: other,
variant: intermediate[port]]];
AddEdge[vs, port];
NoteNewPart[im];
};
NoteNewPart:
PROC [v: Vertex] = {
ct: CellType = v.containingCT;
pbn: Mapper = NARROW[Asserting.FnVal[partsByNameKey, ct.otherPrivate]];
PerName:
PROC [assertion: Asserting.Assertion] = {
name: ROPE = NARROW[Asserting.TermsOf[assertion].first];
SELECT pbn.Map[name]
FROM
NIL => IF pbn.SetMapping[name, v] THEN ERROR;
v => NULL;
ENDCASE => ERROR;
};
IF pbn = NIL THEN RETURN;
Asserting.EnumerateAssertionsAbout[nameReln, v.other, PerName];
};
CreateCellType:
PUBLIC
PROC [design: Design, cellTypeName:
ROPE, class: CellClass, internals:
BOOL, otherPublic, otherPrivate: Assertions ←
NIL]
RETURNS [ct: CellType] = {
pbn: Mapper = CreateHashDictionary[TRUE];
ct ←
NEW [CellTypePrivate ← [
class: class,
designs: CreateHashSet[],
publicKnown: TRUE,
privateKnown: TRUE,
otherPublic: Asserting.Assert[nameReln, LIST[cellTypeName], otherPublic],
otherPrivate: otherPrivate
]];
[] ← AddPort[[parent: ct]];
IF internals
THEN {
iw: Wire;
ct.otherPrivate ← Asserting.AssertFn1[partsByNameKey, pbn, ct.otherPrivate];
ct.asUnorganized ←
NEW [UnorganizedPrivate ← [
containedInstances: CreateHashSet[]
]];
iw ← CreateWire[ct];
IF ct.asUnorganized.internalWire # iw THEN ERROR;
AddMirror[ct];
};
[] ← design.cellTypes.UnionSingleton[ct];
[] ← ct.designs.UnionSingleton[design];
};
CreateArray:
PUBLIC
PROC [design: Design, cellTypeName:
ROPE, class: CellClass, eltType: CellType, size, jointsPeriod: Size2, borders:
ARRAY Dim
OF
ARRAY End
OF
NAT, otherPublic, otherPrivate: Assertions ←
NIL]
RETURNS [ct: CellType] = {
nj: INT = jointsPeriod[Foo] * jointsPeriod[Bar];
gps: GroupingParmses = [
Foo: ComputeGroupingParms[size[Foo], jointsPeriod[Foo], borders[Foo]],
Bar: ComputeGroupingParms[size[Bar], jointsPeriod[Bar], borders[Bar]]];
middlea: Range2 = [gps[Foo].middle, gps[Bar].middle];
ngi: NAT = gps[Foo].sum * gps[Bar].sum;
a: Array =
NEW [ArrayPrivate ← [
eltType: eltType,
prevArray: eltType.lastArray,
nextArray: NIL,
size: size,
jointsPeriod: jointsPeriod,
groupingParmses: gps,
groupingses: CreateRefSeq[ngi],
toRole: [[CreateRefTable[], CreateRefTable[]], [CreateRefTable[], CreateRefTable[]]],
roles: [CreateVarRefSeq[], CreateVarRefSeq[]],
joints: [CreateRefSeq[nj], CreateRefSeq[nj]],
toWire: CreateRefTable[],
wires: CreateHashSet[],
portWire: CreateRefTable[]
]];
tf: INT = a.jointsPeriod[Foo];
tb: INT = a.jointsPeriod[Bar];
ct ← CreateCellType[design, cellTypeName, class, FALSE, otherPublic, otherPrivate];
ct.asArray ← a;
IF a.prevArray # NIL THEN a.prevArray.asArray.nextArray ← ct ELSE eltType.firstArray ← ct;
eltType.lastArray ← ct;
eltType.useCount ← eltType.useCount + 1;
FOR gi:
NAT
IN [0 .. ngi)
DO
a.groupingses[gi] ←
NEW [GroupingsPrivate ← [
toGroup: CreateRefTable[],
groups: CreateHashSet[]
]];
ENDLOOP;
FOR d: Dim
IN Dim
DO FOR
f
f:
INT
IN [0 ..
t
f)
DO
FOR
f
b:
INT
IN [0 ..
t
b)
DO
phase2: Nat2 = [ff, fb];
rawLair: Range2 =
SELECT d
FROM
Foo => [[0, a.size[Foo]-1], [0, a.size[Bar]-0]],
Bar => [[0, a.size[Foo]-0], [0, a.size[Bar]-1]],
ENDCASE => ERROR;
jiir: Range2 = Range2Div[r: rawLair, t: jointsPeriod, f: phase2];
size2: Size2 = RangeShape[jiir];
i: INT = ArrayJointIndex[a, phase2];
middlej: Range2 = Range2Div[r: ShaveRange2Top1[middlea, d], t: jointsPeriod, f: phase2];
jgps: GroupingParmses = [
Foo: ComputeJGP[jiir[Foo], middlej[Foo]],
Bar: ComputeJGP[jiir[Bar], middlej[Bar]]];
njgi: NAT = jgps[Foo].sum * jgps[Bar].sum;
j: Joint = a.joints[d][i] ←
NEW [JointPrivate ← [
size2: size2,
size: size2[Foo]*size2[Bar],
groupingParmses: jgps,
ties: CreateRefSeq[njgi],
toTie: [CreateRefSeq[njgi], CreateRefSeq[njgi]]
]];
FOR jgi:
NAT
IN [0 .. njgi)
DO
j.ties[jgi] ← CreateHashSet[];
j.toTie[low][jgi] ← CreateRefTable[];
j.toTie[high][jgi] ← CreateRefTable[];
ENDLOOP;
design ← design;
ENDLOOP ENDLOOP ENDLOOP;
};
ComputeGroupingParms:
PROC [size, jointsPeriod:
NAT, borders:
ARRAY End
OF
NAT]
RETURNS [gp: GroupingParms] = {
peculiar: NAT = borders[low] + borders[high];
IF peculiar >= size
THEN
RETURN [[
middle: [size, size],
firstHigh: size,
sum: size,
d: 0]];
{firstHighGI: NAT = borders[low] + jointsPeriod;
firstHighI: NAT = size - borders[high];
gp ← [
middle: [borders[low], firstHighI],
firstHigh: firstHighGI,
sum: peculiar + jointsPeriod,
d: firstHighGI - firstHighI];
RETURN [gp];
}};
ComputeJGP:
PROC [jiir, middle: Range]
RETURNS [gp: GroupingParms] = {
hasMiddle: BOOL = middle.maxPlusOne > middle.min;
nMid: NAT = IF hasMiddle THEN 1 ELSE 0;
nHigh: NAT = jiir.maxPlusOne - middle.maxPlusOne;
nLow: NAT = middle.min - jiir.min;
peculiar: NAT = nLow + nHigh;
firstHigh: NAT = nLow + nMid;
IF jiir.min # 0 THEN ERROR;
gp ← [
middle: middle,
firstHigh: firstHigh,
sum: peculiar + nMid,
d: firstHigh - middle.maxPlusOne
];
RETURN [gp];
};
KnowVertexName:
PUBLIC
PROC [v: Vertex, name:
ROPE] = {
ct: CellType = v.containingCT;
pbn: Mapper = NARROW[Asserting.FnVal[partsByNameKey, ct.otherPrivate]];
IF pbn #
NIL
THEN {
SELECT pbn.Map[name]
FROM
v => RETURN;
NIL => IF pbn.SetMapping[name, v] THEN ERROR;
ENDCASE => ERROR;
};
v.other ← Asserting.Assert[nameReln, LIST[name], v.other];
};
DeleteVertex:
PUBLIC
PROC [v: Vertex] = {
ct: CellType = v.containingCT;
pbn: Mapper = NARROW[Asserting.FnVal[partsByNameKey, ct.otherPrivate]];
PerName:
PROC [assertion: Asserting.Assertion] = {
name: ROPE = NARROW[Asserting.TermsOf[assertion].first];
IF NOT pbn.SetMapping[name, NIL] THEN ERROR;
};
Killit:
PROC [p: Port, w: Vertex, e: Edge] = {
RemoveEdge[e];
WITH w
SELECT
FROM
ci: CellInstance => NULL;
im: Intermediary => IF w = e.sides[wireward].v THEN DeleteVertex[w];
wire: Wire => NULL;
ENDCASE => ERROR;
};
EnumerateImmediateEdges[v, Killit];
WITH v
SELECT
FROM
ci: CellInstance => {
IF ci.nextInstance # NIL THEN ci.nextInstance.prevInstance ← ci.prevInstance ELSE ci.type.lastInstance ← ci.prevInstance;
IF ci.prevInstance # NIL THEN ci.prevInstance.nextInstance ← ci.nextInstance ELSE ci.type.firstInstance ← ci.nextInstance;
v.containingCT.asUnorganized.containedInstances.RemoveElt[ci];
ci.type.useCount ← ci.type.useCount - 1;
};
im: Intermediary => NULL;
w: Wire => {
IF w.next # NIL THEN w.next.prev ← w.prev ELSE w.containingWire.lastChild ← w.prev;
IF w.prev # NIL THEN w.prev.next ← w.next ELSE w.containingWire.firstChild ← w.next;
};
ENDCASE => ERROR;
IF pbn # NIL THEN Asserting.EnumerateAssertionsAbout[nameReln, v.other, PerName];
};
IsMirror:
PUBLIC
PROC [v: CellInstance]
RETURNS [isMirror:
BOOL] = {
isMirror ← v.type = v.containingCT;
};
AddMirror:
PUBLIC
PROC [lct: CellType] = {
CreateMirrorBinding:
PROC [port: Port, cellward: Vertex] = {
FOR subPort: Port ← port.firstChild, subPort.next
WHILE subPort #
NIL
DO
subVertex: Vertex;
IF subPort.wire #
NIL
THEN {
AddEdge[[cellward: cellward, wireward: subPort.wire], subPort]}
ELSE {
subVertex ← CreateIntermediary[cellward, wireward, lct, subPort, Asserting.Filter[nameReln, subPort.other].about];
CreateMirrorBinding[subPort, subVertex];
}
ENDLOOP;
};
v: CellInstance =
NEW [VertexPrivate.cell ← [
containingCT: lct,
other: Asserting.Assert[nameReln, LIST[R["mirror"]], NIL],
variant: cell[type: lct--AM2 says not to link it--]
]];
lct.asUnorganized.mirror ← v;
CreateMirrorBinding[lct.port, v];
};
VarRefSeqAppend:
PUBLIC
PROC [vrs: VarRefSeq, value:
REF
ANY] = {
IF vrs.length = vrs.refs.length
THEN {
oldRefs: RefSeq = vrs.refs;
vrs.refs ← CreateRefSeq[MAX[oldRefs.length*2, 1]];
FOR i:
INT
IN [0 .. oldRefs.length)
DO
vrs.refs[i] ← oldRefs[i];
ENDLOOP;
};
vrs.refs[vrs.length] ← value;
vrs.length ← vrs.length + 1;
};
FloorDiv:
PUBLIC
PROC [num, den:
INT]
RETURNS [quot:
INT] = {
IF den < 0 THEN {den ← -den; num ← -num};
IF num < 0 THEN num ← num - (den-1);
quot ← num/den;
};
CeilDiv:
PUBLIC
PROC [num, den:
INT]
RETURNS [quot:
INT] = {
IF den < 0 THEN {den ← -den; num ← -num};
IF num > 0 THEN num ← num + (den-1);
quot ← num/den;
};
Choose2:
PROC [n:
INT]
RETURNS [nChoose2:
INT] =
INLINE {
nChoose2 ← n*(n-1)/2};
Log:
PUBLIC
PROC [fmt:
ROPE, v1, v2, v3, v4, v5:
REF
ANY ←
NIL] = {
DO
IF log = NIL THEN log ← ViewerIO.CreateViewerStreams["Lichen Debugging Log"].out;
log.PutF[fmt, [refAny[v1]], [refAny[v2]], [refAny[v3]], [refAny[v4]], [refAny[v5]] !IO.Error => IF ec = StreamClosed THEN {log ← NIL; LOOP}];
EXIT;
ENDLOOP;
};
log: IO.STREAM ← NIL;
END.